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This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced...
Field programmable gate arrays (FPGAs) have emerged as platform of choice for efficient hardware realization of computation intensive algorithms because of their intrinsic parallelism and flexible architecture. However, to achieve high performance, FPGA must be supported by efficient design methodology and optimization techniques. In this paper, FPGA-based design methodology and optimization techniques...
Algorithms used in signal and image processing applications are computationally intensive. For optimized hardware realization of such algorithms with efficient utilization of available resources, an in-depth knowledge of the targeted field programmable gate array (FPGA) technology is required. This paper presents an overview of the architectures and technologies used in modern FPGAs. A case study...
The design and field programmable gate array (FPGA)-based realisation of automatic censored cell averaging (ACCA) constant false alarm rate (CFAR) detector based on ordered data variability (ODV) is discussed here. The ACCA-ODV CFAR algorithm has been recently proposed in the literature for detecting radar target in non-homogeneous background environments. The ACCA-ODV detector estimates the unknown...
Matrix multiplication is a computation intensive operation and plays an important role in many scientific and engineering applications. For high performance applications, this operation must be realized in hardware. This paper presents a parallel architecture for the multiplication of two matrices using field programmable gate array (FPGA). The proposed architecture employs advanced design techniques...
In this paper we present hardware realization of a novel Automatic Censored Cell Averaging (ACCA) Constant False Alarm Rate (CFAR) detection algorithm based on Ordered Data Variability (ODV) using Field Programmable Gate Array (FPGA). This algorithm has been recently proposed in the literature for radar target detection in non-homogeneous environments. The unknown background level can be estimated...
Fourth-order cross moments are used in modern digital signal processing as a powerful analytical tool for the synthesis and analysis of signals and systems. Computing fourth-order cross moments from incoming time-series data is computationally intensive process and requires fast computing systems and parallel processing techniques to meet the real time processing requirement. An algorithm based on...
In this paper, behavioural model of a dual cascaded phase locked loop (PLL) based frequency synthesizer is presented and the results are validated through SystemVision simulation using very high speed Integrated circuit hardware description language-analog mixed signal (VHDL-AMS). Dual cascaded PLL consists of a low jitter PLL employing a voltage controlled crystal oscillator (VCXO) followed by a...
Arbitrary waveform generators (AWGs) are becoming increasingly important for test and measurement applications. This paper describes a new approach for generating arbitrary waveforms using FPGA and a set of Rademacher and Walsh functions. Utilizing these orthogonal functions, any periodic waveform can be realized. Recent advancements in field programmable gate array (FPGA) technology have made waveform...
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