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DC numerical simulations of a Double-Gate (DG) MOSFET are performed including self-heating. Considering proper thermal conductivity, hydrodynamic model and optimizing pads, the resulting maximum lattice temperature of the transistor is 345 K, being located in channel layer, at the drain extension.
In the last years the MOS transistor technology has reach very high cut-off frequencies (near to 500 GHz), thanks to the continuous reduction of the channel length, but the short-channel-effects (SCE) strongly affects the MOSFET behavior below 60 nm. For such technology nodes the Multiple-Gate transistor (MuGFET) appears as a promising alternative to continue with the International Technology Roadmap...
In this paper we present the 3D trapezoidal structure for analyzing FinFET MOSFETs using three different mesh regions, one at the top and two in the sidewalls of the fin, which allows the consideration of different carrier mobility at each region due to crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed. Validation...
Gate current present in double-gate fully depleted MOSFETs can significantly contribute to its measured channel current. For this reason the presence of direct tunneling and GIDL effects on the total gate and drain currents of Fin-FETs with different dimensions is analyzed. To fulfill this task, expressions for the leakage current due to direct tunneling and GIDL effects at the metal-gate/high-k structure...
A compact model for small-signal equivalent circuit of DG-MOSFETs is presented. The intrinsic parameters are obtained from DC analytic compact model. This DC model allows determining the mobile charge inside the transistor channel, from which the intrinsic parameters are derived. Additionally, the extrinsic capacitances are calculated and included into the model. This compact small-signal model allows...
In this paper we present a new approach of analyzing 3D structure for Triple-Gate MOSFETs with three different mesh regions, one at the top and two in the sidewalls of the fin, which allows the consideration of different carrier mobility at each region due to the crystalline orientation and technological processing. A procedure for the extraction of the mobility parameters in each region is developed...
The harmonic distortion (HD) exhibited by unstrained and biaxially strained fin-shaped field-effect transistors operating in saturation as single-transistor amplifiers has been investigated for devices with different channel lengths L and fin widths Wfin. The study has been performed through device characterization, 3-D device simulations, and modeling. Nonlinearity has been evaluated in terms of...
In this paper the gate leakage current in metal-oxide-semiconductor (MOS) is studied in order to find promising materials for the 22 nm node in double gate MOSFETs by considering simple and improved analytical models of the direct tunneling current by using proper WKB tunneling probability through gate oxide.
The gate current present in double-gate fully depleted MOSFETs can significantly contribute to the channel current measured in these devices. For this reason, models must take account of this effect in order to represent correctly the behavior of the devices. In this paper, we report a complementation to the symmetric doped double gate model for MOSFETs, by including the presence of gate tunneling...
A compact explicit model for undoped Double-Gate (DG) SOI MOSFET including velocity saturation is presented. Using this model, intermodulation linearity obtained from device level Harmonic Balance (HB) simulation and Integral Function Method (IFM) are compared.
We present a Verilog-A implementation of an Improved Charge Sheet Model (ICSM) for PD SOI MOSFETs. This model is a physical and continuous compact model for deep-submicron transistors focused in an accurate description of high order derivatives, in order to obtain good approximation of the harmonic distortion behavior. The implementation of the model, using Verilog-A language, allows analog circuit...
Double-gate MOS transistors and their vertical version, FinFETs, are very promising for integrated circuit low signal analog applications. In this paper we present, for the first time, the nonlinearity analysis of this type of devices which complements the already done studies about the advantages and possibilities of FinFET for analog application. The analysis was done using the transfer DC characteristics...
In this paper the linearity of asymmetric channel double-gate transistors, using the graded-channel (GC) configuration and gate-all-around architecture, operating as an amplifier, is studied in terms of lightly doped region length. The total harmonic distortion and third-order harmonic distortion are used as figures of merit. The results are compared with single-gate transistors with similar channel...
In this paper an evaluation of the harmonic distortion of graded-channel SOI nMOSFETs is performed. The analysis is carried out by comparing an analytical continuous model and experimental results. The total harmonic distortion, as well as the third and second order terms are used as figures of merit in this comparison. It is shown that GC SOI devices present better gain and linearity behavior than...
The modeling of MOSFET I-V curves for distortion analysis in analog circuit design requires compact models for both long and short channel devices, which describe the transistor behavior with high precision based on the physics of the device. In the present paper, to achieve such precision, modifications of the EKV model equations are presented, while using the same parameters. A comparison for PD...
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