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Multimedia streaming applications have stringent Quality-of-Service (QoS) requirements. Typically, each packet is associated with packet delivery deadline. We are interested in designing feedback-based adaptive network coding schemes with the aim of minimizing decoding delay and video distortion in wireless broadcasting networks over the packet-erasure channel. In this paper, we first introduce the...
It's known that the bit errors of polar codes with successive cancellation (SC) decoding are coupled. We call the coupled information bits the correlated bits. In this paper, concatenation schemes are studied for polar codes and LDPC codes. In a conventional concatenation scheme, to achieve a better BER performance, one can divide all bits in a LDPC block into polar blocks to completely de-correlate...
3G systems, which are expected to still be widely deployed over the next decade, utilize Direct-Sequence Code-Division Multiple-Access (DS-CDMA) which suffers mainly from the Multiple Access Interference (MAI). This paper proposes improved decoder log-likelihood ratios for the practical uplink. The basic idea is to utilize knowledge about user cross-correlations and fading coefficients to obtain conditional...
In-situ timing error detection and correction mechanisms (such as Razor) monitor the performance of actual datapaths, and are believed more resilient in adaptive voltage scaling (AVS) systems, especially when considering local variations. However, Razor has serious hold time problems, of which the overwhelming buffer padding makes it infeasible in advanced process technologies. Pre-error (or in-situ...
Real-time video applications, such as multi party video conferencing, involve the simultaneous transport of multiple and potentially multi-layered video sources to participating or interested parties. It is desirable to mix these multiple source videos into a single video stream at intermediary nodes in the network, e.g. at Multipoint Control Units (MCU). This has the advantage of reduced application...
BiCMOS technology is necessary to develop a large capacity SRAM with a high operating speed approximating that of a bipolar ECL RAM. Conventional BiCMOS circuits(1) can not obtain high speed operation as bipolar circuits, because the logic swing and circuit stages are large. However, using conventional bipolar circuits for the SRAM peripheral circuits results in large power dissipation. In this paper,...
We analyze deterministically constructed (i.e., non-ensemble-based) codes in the waterfall and error floor region. The analysis directly applies to several FEC classes proposed for high-speed OTNs such as staircase and braided codes.
A low-jitter and wide output frequency range ADPLL was proposed in this paper. The adopted PDF based on sense-amplifier flip-flop (SAFF) can effectively improve the jitter performance. The novel DCO with cascading structure consists of a coarse-tuning delay chain and a fine-tuning interpolator, obtaining both wide frequency tuning range and high resolution. A high-resolution TDC was employed in this...
In order to reduce the outage probability of cooperative communication, a hybrid forwarding HARQ scheme in wireless network is proposed. In this scheme, if the relay decoding unsuccessfully until the last time, the Amplify-and-Forward protocol will be used to retransmit. Otherwise, the code cooperation will be used. Both of the Chase Combining and Incremental Redundancy combining is used in this scheme...
A networked controlled system (NCS) in which the plant communicates to the controller over a channel with random delay loss is considered. The channel model is motivated by recent development of tree codes for NCS, which effectively translates an erasure channel to one with random delay. A causal transform coding scheme is presented which exploits the plant state memory for efficient communications...
The high quality and low delay video streaming is desired for all users. Especially the playback delay is much more undesirable since it is easily perceived by human eyes, and it consists of decoding delay and transfer delay. In this paper we use High Efficiency Video Coding (HEVC) with tiles to achieve parallel encoding/transmission/decoding, and propose to use a novel adaptive tile boundary (ATB)...
In echo-based audio watermarking methods, poor robustness and low embedding capacity are the main problems. In this paper, we propose a novel time-spread echo method for audio watermarking, aiming to improve the robustness and the embedding capacity. To improve the robustness, we design an efficient pseudonoise (PN) sequence and a corresponding decoding function. Compared to the conventional PN sequence...
As the microelectronics technology continuously scales down, the probability of multiple cell upsets (MCUs) induced by radiation in memory devices increases. It is required a robust error correction code (ECC), that has also an area, energy-efficient silicon implementation, to protect electronic devices from MCUs. This article describes the conception, implementation, and evaluation of a new algorithm...
Watermarking, known as a typical active network traffic analysis technique, has been widely used in stepping stone detecting and anonymity tracing. Among several different watermarking schemes, the interval centroid based watermarking scheme has shown its robustness in the problems such as chaff packet, packet drops and repacketization. It can be widely used in many applications, for it embeds watermarking...
This paper analyzes the spectral efficiency, probability of a lost block and average delay performances of the generic Repetition Redundancy (RR) and Incremental Redundancy (IR) truncated Hybrid-Automat Repeat reQuest (H-ARQ) algorithms on block-faded Rayleigh channels. The analysis presents the derivation of the three performance metrics' expressions, using an intermediate performance metric called...
Reversible logic is an emerging technology with wide spread applications in the field of digital systems. The term RAM refers to memory that is accessed with an address and has latency independent of address. In semiconductor memories RAM usually refers to volatile memory read/write memory as opposed to ROM (read only memory). The 2n×2m×1 RAM has n rows and m columns, out of which one bit is selected...
A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on FPGA platforms Spartan-3 have been used for...
This paper proposes a fully Digital, Analog-to-Digital Converter (FD-ADC) which is designed by using UMC's 180 nm digital CMOS technology. The advantages of the digital ADC are its simplicity and low complexity. Power dissipation is also very less compared to other ADC architectures. The FD-ADC is suitable for low power applications and where the input signal swing is small. FD-ADC also needs very...
Three potential interference cancellation schemes are compared for the application to a non-orthogonal multiple access communication system. One is the conventional hard successive interference cancellation (SIC) scheme based on independent single-user decodings. The other two, proposed in this paper, are a soft-in soft-out parallel interference cancellation (SISO-PIC) and a hybrid interference cancellation...
In joint source-channel arithmetic coding, a forbidden symbol (FS) is added to the symbol set to make it more robust against transmission errors. By splitting the interval occupied by the FS into subintervals, various configurations are possible. In this paper, the delay probability function (DPF), the probability of the number of bits required to detect an error, is calculated for various FS configurations...
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