Reversible logic is an emerging technology with wide spread applications in the field of digital systems. The term RAM refers to memory that is accessed with an address and has latency independent of address. In semiconductor memories RAM usually refers to volatile memory read/write memory as opposed to ROM (read only memory). The 2n×2m×1 RAM has n rows and m columns, out of which one bit is selected as an output. The design of proposed ram requires write/read enabled FF for information read and write and address decoding circuit. The paper uses the reversible modified Frekdin gate to propose an address decoder and write enabled master slave D FF. The proposed designs are optimized in terms of quantum cost. The proposed designs are used for implementation of 2n×2m×1 reversible RAM. Several theorems related to Decoders and 2n×2m×1 reversible RAM are suggested and proved.