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The memristor device has emerged as the missing fourth fundamental circuit element after resistor, inductor and capacitor. Various implementations of memristors have been reported, with the one using a TiO2 layer sandwiched between two platinum electrodes considered to be most promising. Because of its very small feature sizes and low power consumption, it is projected to replace CMOS technology in...
The application of sensor networks varies from medical field to the military application. The raw data onto the sensor node is of large quantity and it is necessary to store these data bits. In this paper, design of optimized Static Random Access Memory (SRAM) array for the sensor application is implemented. SRAM cell is designed using 8T. The Half Select Condition Free Cross Point 8T SRAM is modified,...
Side channel attacks exploit inadvertent information leakage from the physical implementation of computing systems, bypassing the theoretical strength of cryptographic algorithms. Of particular concern are software side-channel attacks which can be mounted remotely without access or alteration of the hardware system. One type of attack that has been demonstrated to be highly effective is cache timing...
A 576-bit LDPC decoder is designed using a charge-recovery logic family and in-package inductors. The decoder testchip is fabricated in a 65nm CMOS flip-chip process. Unlike all previously published high-performance charge-recovery chips, which use on-chip inductors to recover charge from parasitic capacitance, this charge-recovery design uses in-package inductors, avoiding the area overheads of on-chip...
This paper presents a new coding scheme that considerably increases the efficiency of the channel in multicast setting. Specifically, we study the scenario where three terminals exchange their messages via a satellite gateway. The main difference between the proposed scheme and conventional three-way relay channel is the use of joint channel and network coding. This allows three terminals to transmit...
In this paper we investigate the problem of information storage in inherently unreliable memory cells. In order to increase the memory reliability, information is stored in memory cells as a codeword of a low-density parity-check (LDPC) code, while the memory content is updated periodically by an error correction scheme. We first present an overview on the state-of-the memory architectures based on...
BCH (Bose-Chaudhuri-Hocquenghem) coding is very useful to detect and correct the errors in communication system and also on-chip (computer) memory systems. This paper presents a High-speed BCH decoder that corrects double-adjacent and single-bit errors in parallel and serially corrects multiple-bit errors instead of double-adjacent errors. Its operation is based on extending an existing decoder that...
The study is mainly intended to solve the problem of Bisha University traditional Combinational Logic Circuits labs in design logic course. This course is one of the prescribed courses in computer science department-semester five. In A set of programmable virtual instruments in the Combinational Logic Circuits (VIs) have been designed and tested Using LabVIEW environment. The aim of this study is...
As modern ASIC technologies suffer from substantial delay uncertainties, delay insensitive (DI) communication protocols are receiving increasing attention. Among these, the more energy-saving 2-phase protocols are most attractive. In the literature such protocols are widely covered already, with Level-Encoded-Dual-Rail (LEDR), Level-Encoded-Transition-Signalling (LETS) and Transition Encoding (TranEnc)...
The implementation of the SubBytes (or S-Box) step of the AES algorithm significantly contributes to the area, delay, and power of AES accelerators. Unlike typical logic gate S-Box implementations, we use full-custom 256×8-bit ROMs, which significantly improve performance and efficiency. We implemented a fully-unrolled, pipelined AES-128 encryption accelerator using ROM-based S-Boxes in 65nm bulk...
Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architectures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed...
Secure Write-Efficient Memory (WEM) was proposed in [11] to solve the endurance and the insecure deletion problems in flash memories. Information theoretical results, i.e., the achievable region and the secrecy rewriting capacity, have been obtained. In this work, a code construction for secure WEM is presented and it is optimal for a large family of secure WEM.
This work addresses the reversible circuit design using novel modularization approach by presenting architecture of a logically reversible processor based on the Von Neumann architecture that can operate with very low power consumption, protection of power analysis attack and long span of life due to less heat dissipation. The organization and architecture of the proposed processor is designed from...
We report the first 25Gb/s 3-level modulated BM-RX employing a ¼-rate linear BM APD-TIA and a custom decoder IC. We successfully demonstrated burst-mode sensitivity of −20.4dBm with 18dB dynamic burst-to-burst for 25Gb/s upstream links.
Marginal failure is common in failure analysis in which the failure is dependant to voltage or timing. Instead of using conventional die top microprobing to isolate the failure location, Laser Assisted Device Alteration (LADA) together with modified test pattern to isolate the failure location by incorporating Atomic Force Probe (AFP) and Transmission Electron Microscopy (TEM) to determine the failure...
Quantum codes excel at correcting local noise but fail to correct leakage faults that excite qubits to states outside the computational space. Aliferis and Terhal have shown that an accuracy threshold exists for leakage faults using gadgets called leakage reduction units (LRUs). However, these gadgets reduce the threshold and increase experimental complexity, and the costs have not been thoroughly...
Register file (RF) memory is important in low power SOCs due to its inherent low voltage stability. Moreover, designs increasingly use compiled instead of custom memory blocks, which frequently employ static, rather than pre-charged dynamic register files. In this paper, we compare static and dynamic RF power dissipation and timing characteristics. The relative timing and power advantages of the designs...
This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used...
In this paper, we first reveal the similarity of polar encoder and fast Fourier transform (FFT) processor. Based on this, both feed-forward and feed-back pipelined implementations of polar encoder are proposed. It is pointed out that the feedback part of SC polar decoder is nothing but a simplified version of polar encoder and therefore can be pipelined implemented also. Moreover, a general approach...
Memristors are emerging as powerful nanoscale devices for diverse applications, such as high-density memories and neuromorphic applications. However, this nascent technology requires considerable advancement before this vision is realized. We present a highly configurable CMOS interface chip which enables the characterization of on-chip memristors, especially for memory applications. The chip was...
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