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Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architectures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed...
We provide the first constructions of a new family of error-correcting codes called “energy-adaptive codes.” These codes are designed to enable adaptive circuit implementations that minimize the total system-level energy based on varying distances and target error probabilities. Recent work has explored fundamental limits and practical strategies for minimizing total (transmit + circuit) power, considering...
We propose without loss of generality strategies to achieve a high-throughput FPGA-based architecture for a binary Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code based on a circulant-1 identity matrix construction. We present a novel representation of the parity-check matrix (PCM) providing a multi-fold throughput gain. Splitting of the node processing algorithm enables us to achieve pipelining...
Partial dynamic reconfiguration of FPGAs can be used to implement complex applications using the concept of virtual hardware. In this work we have used partial dynamic reconfiguration to implement a JPEG decoder with reduced area. The image decoding process was adapted to be implemented on the FPGA fabric using this technique. The architecture was tested in a low cost ZYNQ-7020 FPGA that supports...
The ARM simulator not only eliminates the barriers of embedded systems' hardware environment, but also improves the efficiency, security and reliability for the development process. To improve the performance of an ARM-based function simulation, a novel simulation framework to the ARM processor is proposed, which is based on the ARM instructions' eigenvalue. Therein, functions of registers, the instruction...
Pattern matching is used in most of the network security devices in order to detect attacks, threats and malicious network traffic. Many hardware architectures have been designed to accelerate this time-critical operation in order to increase processing speed and achieve multi-gigabit throughput. Recently introduced automata processor is an powerful architecture which represents a new class of field...
Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall...
With the increasing volume of business the civil aviation data processing system, the data processing efficiency requirements become higher and higher. In order to improve the speed of data processing, we design a parallel scheme of GRIB according to the GRIB data processing flow. We achieved the parallel processing of GRIB data reading and decoding process, and carried out the related test. It is...
Previously, various rectification methods using compressed lookup table have been studied for real-time hardware stereo vision system. These loss compression methods may occur distortion that could corrupt disparity estimation process. Differentially encoded lookup table method which is lossless compression has no distortion with reasonable compression ratio. However, the method is limited to low-resolution...
The Hybrid Memory Cube (HMC) is a promising alternative to DDRx memory due to its potential to achieve significantly higher bandwidth. However, the high static power of an HMC device compromises power efficiency when the device is lightly utilized. Activating a sleeping HMC takes over 2µs, which makes it challenging to manage HMC power without a substantial degradation in system performance. We introduce...
High-speed and low-area decoders for low-density parity-check (LDPC) codes with very long block lengths are challenging to implement due to the large amount of nodes and edges required. In this paper we implement a decoder for a (32643, 30592) LDPC code that has variable nodes of degree 7, check nodes degrees of 111 and 112, and 228501 edges, making fully-parallel hardware implementation unfeasible...
In future 5G mobile networks, radio access network functions will be virtualized and implemented on centralized cloud platforms. In principle, this allows for more advanced algorithms of joint processing and offers the ability to balance the computational load. However, the shift of functionality on a cloud-platform also imposes challenges on the design of the applied algorithms. In this paper, we...
Data conversion operations are important and essential part of floating point units in a processor and typical instructions include conversion between various precisions, integer to floating point and vice versa, floating point to fixed point and vice versa etc. Besides few processors have instructions to round and truncate data, sign injections, move data between co-processors registers and general...
This paper first proposes two new LDPC decoding algorithms that may be seen as imprecise versions of the Offset Min-Sum (OMS) decoding: the Partially OMS, which performs only partially the offset correction, and the Imprecise Partially OMS, which introduces a further level of impreciseness in the check-node processing unit. We show that they allow significant reduction in the memory (25% with respect...
With scaling of process technologies and increase in process variations, embedded memories will be inherently unreliable. In this paper, we propose redundancy-free adaptive error-correcting codes for the noisy min-sum decoder subject to memory errors. We consider the popular memory error model with a binary symmetric channel. We first revisit the density evolution analysis proposed by Balatsoukas-Stimming...
Transient and permanent errors in memory and CPUs occur with alarming frequency. Although most of these errors are masked at the hardware level or result in crashes, a non-negligible number of them leads to Silent Data Corruptions (SDCs), i.e., incorrect results of computations. Safety-critical programs require a very high level of confidence that such faults are detected and not propagated to the...
This paper proposes a new efficient bypass coding scheme (EBCS) based on Logarithmic Binary Arithmetic Coding (LBAC). The bypass coding model is used to encode a symbol which has equal probability (0.5). The percentage of the bypass coding model is about 25 in CABAC of H.265/HEVC. The proposed EBCS provides a hardware-efficient design that can significantly increase the processing speed, and it has...
Polar codes are the first error-correcting codes to provably achieve the channel capacity but with infinite code-lengths. For finite codelengths the existing decoder architectures are limited in working frequency by the partial sums computation unit. We explain in this paper how the partial sums computation can be seen as a matrix multiplication. Then, an efficient hardware implementation of this...
Stochastic decoding can be applied to Low-Density Parity-Check codes in order to achieve high throughput with less area. However, most architectures suffer from large decoding latencies, due to the mechanism of stochastic computation. In this paper, three novel strategies, including the LUT-based initialization, the posterior-information-based hard decision and the Bit-Flipping-based post processing,...
As the reliability of NAND Flash memory keeps degrading, Low-Density Parity-Check (LDPC) codes are widely proposed to extend the endurance of Solid State Drive (SSD). However, implementing powerful decoding algorithm such as soft min-sum algorithm with high decoding speed comes along with higher hardware cost. To achieve efficient hardware cost, we propose a multi-strategy ECC scheme which consists...
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