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In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode quaternary logic, is proposed. The dynamic quaternary inverter and literal circuits are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The proposed circuits have some...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
In this paper, a 5.8-GHz active mixer with the low-power and the high conversion gain is designed and fabricated in the TSMC 0.18-μm CMOS 1P6M process. The gate-driven circuit topology and the weak-inversion biasing techniques are employed to implement this mixer, and then achieve the power consumption of 1.13 mW (core circuit), the conversion gain of 8.62 dB, the LO driving power of −3 dBm, and the...
A full -wave CMOS rectifier is presented in this paper which is used for powerlessly power up low voltage biomedical implantable devices. Bootstrapped capacitors are used to decrease the effective threshold voltage of main switch transistor in the rectifier architecture. This architecture has low voltage drop and good overall efficiency even at very low input voltage and over a wide range of frequency...
DRAM chip industry became one of the most researchers' interests nowadays for its simple structure and low power consumption. As the density of DRAM chips increased, many problems occurred that affected the DRAM performance. One of these problems is the increase in the bit-line parasitic capacitance values. These large values slow down the reading operation of the cell and increase the consumed power...
A 24-GHz transformer-based stacked-FET power amplifier (PA) was designed in 90-nm CMOS technology. The stack configuration overcomes the low breakdown voltages of scaled transistors. The proposed power amplifier achieves a saturated output power of 21.7 dBm and 1-dB compressed output power (OP1dB) of 18.9 dBm with peak power-added efficiency (PAE) of 16.7% at 3-V supply voltage. The chip occupies...
This manuscript explores the output phase imbalance observed in the common-gate common-source transistors, and gives a mathematical formulation in determining the length of the compensation transmission line. To demonstrate the validity of this wideband phase-compensation technique, a DC-50GHz active balun is designed using commercial 90nm-CMOS process and then measured, where the phase imbalance...
This paper summarizes the developments of millimeter-wave (mmW) CMOS power amplifiers (PAs) at University of Electronic Science and Technology of China in recent years. Harmonic control technology and inverse Class F technique are used to improve the power added efficiency (PAE) for mmW CMOS PAs effectively. Moreover, by realizing symmetrical voltage coupling between transformer primaries and secondary...
This paper presents a fully integrated BPSK (Binary Phase Shift Keying) Transmitter Front End for Ultra-Wideband (UWB) applications, designed in 130 nm CMOS technology. A simple architecture based on parallel pulse generator blocks in parallel is proposed to produce 9th derivative Gaussian pulses. In addition to the pulse generator, the circuit comprises a passive balun circuit, a common source amplifier,...
This paper presents a fully integrated 60 GHz double-balanced Gilbert cell up-conversion mixer implemented in 90 nm LP CMOS technology. The mixer has been designed for very low DC power consumption (11 mW) and wideband performance to cover the four channel bands of the IEEE802.15.3c standard. Due to measurement limitations different transformers have been designed for IF, LO and RF path to facilitate...
In the presented paper we examine and compare different adder structures for their EMC behavior. On the one hand the analysis is carried out for different topologies as Ripple Carry Adder and Kogge Stone Adder. And on the other hand these topologies are realized in different logic styles as standard CMOS, complementary pass transistor logic, buffered NMOS pass transistor and complementary buffered...
In this paper continuous time high-performance current mirrors (CMs) based on series and parallel connected unity sized CMOS transistors suitable for low power applications are presented. It is shown that the proposed implementation techniques allow an increased output resistance, from twice the output resistance of the simple current mirror (SCM) up to more than 50 times of the cascode current mirror's...
Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and radio frequency identification bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to recharge the batteries while at the same time dramatically decreasing the device leakage currents. The...
This paper presents an integrated bandgap reference circuit which is addressing low current consumption and a wide supply voltage range, using a current mode structure. Embedded in a sophisticated Power Management Unit (PMU) for a GNSS receiver, this bandgap reference has an output of 0.60 V and it can reach a temperature coefficient of 33 ppm/°C in the range from −40 °C to 125 °C. With a 1.4 V supply...
This work presents the circuit level design of a non-volatile D-latch (NVDL) using memristor that retains the stored data in the event of power interruption. The programming complexity of proposed NVDL, unlike previous NV latches, is simplified. The proposed NVDL is designed using 32nm node and results are compared with the volatile CMOS based D-latch. Simulation results show that the proposed NVDL...
With the emergence of energy-starved systems like wireless sensor nodes, it becomes much more of a necessity for important blocks in such systems like the voltage reference (VR) to work at an ultra-low power consumption. Furthermore, the varying requirements of the functional blocks of a wireless sensor node (WSN) entail varying VR requirements, therefore flexibility in the design of VRs is required...
Local field potentials (LFPs) contain relevant information about neuronal population activity [1]. They are commonly measured in the brain to investigate information processing by neural circuits and for neuroprosthetics applications. We present a novel method allowing for in vivo ‘electrical imaging’ of LFPs. An oxide-insulated neural probe was implanted in the brain of a rat, establishing a capacitive...
The application of sensor networks varies from medical field to the military application. The raw data onto the sensor node is of large quantity and it is necessary to store these data bits. In this paper, design of optimized Static Random Access Memory (SRAM) array for the sensor application is implemented. SRAM cell is designed using 8T. The Half Select Condition Free Cross Point 8T SRAM is modified,...
In this paper, a simple filter topology that can be used to implement first-order MOS-only allpass filter is proposed. The proposed MOS-only allpass filter offers inherently very accurate magnitude and phase characteristics at very high frequencies. However, MOS-only active filter suffers from an inherent low frequency limitation. In order to address this issue, the modification technique allowing...
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