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We describe a silicon photonic optical modulator based on a MOS-capacitor and a low power 1V CMOS inverter-based driver IC. In an MZI configuration, this efficient modulator and driver IC combination can produce a 9dB extinction ratio at 28 Gbps, at a wavelength of 1310nm.
This paper deals with the design of a SAR-ADC with 8-bit resolution suited for bio-medical application. The design of the key components of the SAR ADC namely, DAC, Comparator and Sample and Hold circuit (S/H) has been carried out using current mode approach with the DAC operating at sub-threshold regime. The input current range is 10nA to 2.57μA with 10nA as the LSB. The circuit has been designed...
Technology scaling driven by the benefit of integration density, high-speed of operation and low-power dissipation, has overcome many barriers over the last four decades. Currently, it is facing even more hurdles, which are more critical than earlier. One of them is variability. Variability is becoming a metric of equal importance as power, delay, and area. This work attempts to perform power and...
Low power consumption has become a highly important concern for the designs. Glitches contribute to the dynamic power which itself is a major portion of the total power consumed by designs. A glitch is an undesired transition that occurs before intended value in digital circuits. A glitch occurs in CMOS circuits due to differential delay at the inputs of a gate. The paper describes a procedure to...
The locally implicit leapfrog scheme has been proposed as one of the signal/power integrity (SI/PI) circuit simulation techniques of an arbitrary shaped power distribution network (PDN) modeled by triangular meshes. This method can perform transient analysis several times faster than the explicit leapfrog scheme by employing a locally implicit scheme instead of the globally explicit leapfrog scheme...
The current paper aims to put forward the arrangement of a new high speed, low power synchronously clocked NOR-based JK flip-flop embracing modified Gate Diffusion Input (GDI) procedure in 45nm technology. The propounded design on comparison with a synchronously clocked NOR-based JK flip-flop employing the traditional CMOS transistors, transmission gates and Complementary Pass-Transistor Logic (CPL),...
This work details a process-portable test chip, fabricated in 65nm CMOS, specifically designed to measure radiation-induced soft error rate (SER) during operation at near-threshold. A variety of SRAM, register file (RF), and digital logic test structures are included that provide a comprehensive assessment of circuit sensitivities to radiation at low VDD. Neutron irradiation measurements of SRAM/RF...
Rigorous mathematical formulation of digital circuits, although accurate, consumes simulation time of a circuit designer who wishes to have a quick investigation of the effect of various device parameters on the electrical response of a circuit. This paper uses simple yet efficient method to calculate the average resistance of the transistors for finding the RC time constant and thereby the transient...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
In this paper, four adiabatic types have been researches with TSMC 0.18μm library, where Vin=1.8V, frequency=1MHz. We have applied the adiabatic logic structure to further reduce the power dissipation of the PBCAM. In traditional CMOS, the power dissipation mainly occurs in the MOS transistor during input data switching, however, the adiabatic logic circuit takes an opposing direction to...
Spin Wave Devices (SWDs) are promising beyond-CMOS candidates. Unlike traditional charge-based technologies, SWDs use spin as information carrier that propagates in waves. In this scenario, the logic primitive for computation is the majority gate. The majority gate has a greater expressive power than standard NAND/NOR gates, allowing SWD circuits to be more compact than CMOS, already at the logic...
A digital-to-transcoductance converter is presented for use with digitally programmable Nauta structure operational amplifiers. The converter architecture consists of parallel connected tri-state CMOS inverters sized in such a way as to present a complete range of transconductance tunability at the expense of linearity and transconductance output range. Our converter architecture is analysed under...
A low-power smart temperature-sensor has developed using a standard 0.18µm CMOS process technology. The sensor utilizes the dependency of the rising time of the output pulse of an inverter, on the drain current when triggered by a fixed frequency square wave signal. The working temperature of the proposed architecture is −40°C to +85°C with the maximum-power dissipation of 4.276µW. The occupied Si...
This paper discusses and shows the use of Nauta operational transconductance amplifiers as integrator elements in a second-order continuous-time delta-sigma ADC. The structure is studied in order to take advantage of its potentially high bandwidth operation and simple inverter-based structure for wide output voltage range in current and future CMOS process. The second-order continuous-time delta sigma...
Analog signal-processing in deep sub-micron technologies poses many challenges arising from both low supply voltage and intrinsic voltage-gain of short channel devices. Class-AB CMOS transconductance obtained by a pair of complementary transistors is a widely used power efficient building block because it has linear v - i characteristics. This is topologically the same as the logic inverter of CMOS...
A 3-D ring oscillator integrated with through silicon vias (TSVs) is designed and fabricated for testing multilayer stacked integrated circuits with TSV. The proposed 3-D ring oscillator consists of 13 stages. 65-nm CMOS dies with two current-starved inverter and via-last TSVs are designed for the five middle layers of 3-D ring oscillator. The two cascaded inverters are connected to the up-side layer...
In this paper, we have proposed a 4-bit 5-GSample/s flash analog-to-digital converter (ADC) for pulse amplitude modulation (PAM) systems. In order to achieve low-power consumptions, digitalized cells for analogue amplifying are developed in the proposed ADC. Digitalized cells reduce power significantly due to using fewer devices as compared to pure analogue designs. A self-biasing circuit is used...
This paper presents a low power clock multiplier circuit to be used in multistandard transceivers. The circuit is based on a delay locked loop (DLL) and can be used to multiply the input clock reference by 2, 3, 4 5 or 6. The offered clock multiplier circuit is targetted for multistandard System-on-Chip's to be used in smart grid communication. For an input clock reference of 32 MHz, the clock multiplier...
In this paper we propose to utilise 3D-stacked hybrid memories as alternative to traditional CMOS SRAMs in L1 and L2 cache implementations and analyse the potential implications of this approach on the processor performance, measured in terms of Instructions-per-Cycle (IPC) and energy consumption. The 3D hybrid memory cell relies on: (i) a Short Circuit Current Free Nano-Electro-Mechanical Field Effect...
Enhanced current drivability of BEOL-process-compatible dual-oxide complementary BEOL-FETs on LSI-interconnects (Fig. 1) with just two additional masks to the state-of-the-art BEOL process is demonstrated, aiming at high-Vbd pre-driver operation. We have developed processes so that IGZO-based NFETs have lower ARon as compared to currently available Si power devices (Fig. 6). We also developed new...
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