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The present paper proposes the comparative power analysis of different logic gates using conventional CMOS Designs and adiabatic clock gating based designs. For achieving high performance, Adiabatic logic gates are designed using CPAL (complementary pass transistor adiabatic logic).The design of INVERTER, NAND and XOR has been simulated and verified. All the circuits have been simulated using 90nm...
In this paper, a simulation study of Carbon Nano Tube Field Effect Transistor inverter performance is presented using the Southampton model. Evaluation of results from this study was made in terms of propagation delay time and total power consumed by the circuit. Tradeoff between these factors has led to the use of power delay product as a good indicator for design purposes. Such indicator plays a...
A Si ultra-thin body (UTB) junctionless field-effect transistor (UTB-JLFET) with LG = 1 nm and LG = 3 nm have been demonstrated by solving the coupled driftdiffusion (DD) and density-gradient (DG) model. The simulation results show that the Si can be used in ultra-short channel device as long as UTB is employed. As UTB is employed, ultra-short channel device does not need to follow an empirical rule...
Basic structure of latch-type SRAM sense amplifier is analyzed and advantages and disadvantages are compared in this paper, then an improved latch-type SRAM sense amplifier is presented. On this basis, a new sense amplifier is proposed, which can access data fast for low voltage and low power SRAM application. The simulation results show that this sense amplifier has advantage over the conventional...
In this presentation we shortly discuss the evolution of Microelectronics into Nanoelectronics, according to the predictions of Moore's law, and some of the issues related with this evolution. Next, we address the requirements of device modeling related with an extreme device miniaturization, such as the band splitting into multiple subbands and quasi-ballistic transport. Physical models are summarized...
The article describes an original technique for TID testing of complex VLSI circuits (microprocessors) based on combined use of parametric and functional control. The resulting dependences obtained in radiation experiment are qualitatively confirmed by circuit simulation.
Low power VLSI demands for the development of promptly design methodologies to reduce the power consumption or power dissipation up to a level. To meet the growing demand, we propose a new low power multiplexer cell by reducing the MOS Transistor count that reduces the serious threshold loss problem. In the proposed circuit we use CMOS technique for designing of ultra low power multiplexer because...
For high performance and higher computational capability in VLSI circuits feature size should be small. As continue scaling down the dimension of transistors in very deep sub-micron regime parameter variation becomes a critical issue. The performance of any logic circuit decreases by variability of parameters hence increasing leakage current. To overcome the variability issue in sub-micron regime...
This paper presents a third order quadrature sinusoidal oscillator based on CMOS/floating gate CMOS (FGCMOS) inverters. The proposed design uses only three CMOS/FGCMOS inverters (6 MOSFETs), three grounded capacitors and two grounded resistors which makes it suitable for fully integrated circuits. The proposed circuit exhibits attractive features such as low component count, low voltage requirement...
Intrinsic noise has been predicted as a limit to CMOS scaling. If this is the case, the effect would be more severe at low supply voltages, such as the ones applied in subthreshold digital circuits. In this work the effect of intrinsic noise in subthreshold digital nanoscale CMOS is analysed for the first time. Key issues such as variability and the actual bandwidth of the studied circuits are taken...
This paper presents experimental data and analyses from the oscillation frequency of CMOS ring oscillators (ROs). The measurements are analyzed in order to separate the coefficient of variation (CV = σ/μ) behavior of both within-die (WID) process variations and Die-to-Die (D2D) process variations. Three different RO's sizes distributed over a total of 96 ROs per chip were measured in 32 different...
This In this paper, we present a new inverter topology in order to decrease the process variability influence on performances of a ring oscillator. Using FDSOI technology, we used the back-gate electrode of the transistor to symmetrize the output of a complementary inverter. This technique will reduce the variability of the inverter and the jitter (i.e. the phase noise) of the ring oscillator. Complementary...
This paper investigates an inductorless technique for bandwidth extension which uses local positive feedback in an optical receiver front-end based on an inverter-based transimpedance amplifier and Cherry-Hooper post-amplifiers. Small feedback inverters create negative resistance that boosts the output resistance of inverter-based amplifiers. Compared to a reference design having a TIA and a three-stage...
This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80...
This paper presents an on-chip common-mode cancellation circuit which increases the immunity to electromagnetic interference (EMI) of integrated CMOS operational amplifiers when EMI is injected into their inputs. The circuits have been designed in the UMC 180nm CMOS technology. Two case studies have been considered: first, the common-mode cancellation circuit has been used in a Miller amplifier and...
The paper presents the comprehensive analysis and evaluation of static adiabatic logic circuits operated by two phase sinusoidal clock signals. The static adiabatic logic has an advantage in the form of reduction in switching energy while comparing with the dynamic adiabatic logic. This advantage is realized due to the fact that the discharging operation at a node happens only when the input signal...
In this paper, a new Ultra low voltage (ULV) logic circuit based on the floating gate structure is presented. In this technique we utilized the bulks of the transistors to speed up the circuit. Using the proposed method, the speed of the circuit enhances by connecting the bulks of the evaluating and recharge devices to the clock, power supply (VDD) and input signals. The simulation results for the...
In this paper, a new equation for frequency of a ring oscillator are proposed. This method is general enough to be used in all types of ring oscillator delay stages. In this proposed technique we are able to calculate the ring oscillator frequency in absence of process parameters such as threshold voltage, GAMMA, THETA etc. In the underlying work, a comparison has been shown between the analytical...
Adiabatic Logic is the most effective technique which is used for implementing of low power digital logic circuits. In this research paper to designed low power Dissipation carry select adder using DFAL 2X1 mux and Diode free adiabatic logic (DFAL) which compare proposed adder circuit with CMOS Technology Designed Adder for low power VLSI Application. In digital electronics, adder is a play important...
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