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Single phase uninterruptible power supply (UPS) has been widely used for a variety of critical load to overcome the disruption in utility power supplies. Wide band gap (WBG) power semiconductor devices, such as Silicon Carbide (SiC) finds its application in UPS systems due to its higher switching frequency, lower losses, and higher power density compared to Si devices. In this paper, a full SiC-based...
The hot-carrier problems are one of the most serious obstacles in making high-density, high-speed VLSI with sub micron geometry. Consequently, the MOSFET device level degradation under DC and AC stress has been investigated intensively in the past few years. However, little work has been carried out on the circuit level1. This paper deals with two new aspects of the circuit behaviors under AC hot-carrier...
The main disadvantage for cascaded multilevel inverter is the high number of switching device it needs in an installation. To reduce total harmonics distortion (THD) of the output waveform, the number of output voltage level has to be increased, hence the higher number of switching devices. This consequently increases the installation cost, inverter size and voltage losses at the load terminals. In...
A standalone 3-phase half-bridge multilevel inverter with simple basic unit cells coupled to solar power generation is proposed. This proposed inverter is able to operate in either charging mode or inverter mode, which is suitable for solar power generation using photovoltaic modules. The active switches (power MOSFET) in this proposed inverter is operating at fundamental or twice the fundamental...
In this paper, an efficient design of a complimentary metal-oxide semiconductor (CMOS) inverter with symmetric switching characteristics is realized using a cuckoo search algorithm (CSA). CSA is an optimization algorithm which is inspired by the brood parasitic behaviour of cuckoos. The performance of the proposed CMOS inverter design using CSA is compared with particle swarm optimization algorithm...
This paper presents, a controller based on dynamic evolution technique to control the three phase power inverter's output for large load changes. Proposed controller methodology is analysis and is tested on three phase inverter in MATLAB/Simulink for star and delta load with balanced and unbalanced combination. This system is also tested for lagging and leading nature of load by connecting an inductor...
This paper designs a photovoltaic (PV) conversion circuit of single phase full bridge and its peripheral control circuit, with STM8S207R8 as the core processor. The primary principle is that the DC is injected to the sole phase full bridge contravariant circuit, then to the exchange of LC filter circuit. The control signal is produced by the main control unit STM8S207R8 sine-wave pulse-width modulation...
Various soft switching inverter topologies have been reported in the literature with the aims of reducing the switching losses and dynamic switching stress. However, lower losses are generally regarded as one of the most significant advantages of the emerging silicon carbide semiconductor devices over the conventional silicon devices. Both routes seem viable to improve the converter efficiency. To...
This paper demonstrates the performance of a 900 V silicon carbide (SiC) power MOSFET operating at 13.56 MHz in a 2 kW resonant inverter targeted for wireless power transfer (WPT) systems. Operating at multi-MHz switching frequency leads to smaller passive components and has the potential to improve power density and reduce weight for weight-sensitive applications. In addition, the advent of wide...
With the emergence of Wireless Power Transfer (WPT) systems in electric vehicle (EV) applications, variety of power electronics converters topologies are implemented. The proper converter design is crucial in these application to be able to handle the high power and frequency operation. This paper presents an optimum design of 40 kHz single-phase H-bridge resonance inverter for wireless EV's charging...
This work proposes high performance of permanent-magnet synchronous motor (PMSM) driver IC integrated with position sensorless scheme and current sensing circuits. The position sensorless scheme is adapted with digital sliding mode observer (SMO) method that has high robust characteristics of motor parameter variations. For current sensing circuits, 10-bit successive approximation (SAR) analog-to-digital...
Full adder cells play a vital role in numerous VLSI circuits. Therefore, design of an energy-efficient full adder which operates reliably in submicron technologies has become a great concern in recent years. Some previously designed cells suffer from non-full swing outputs, high-power consumption and low-speed issues. In this paper, two high-speed, low-power and full-swing full adder circuits are...
Memristors can be optimally used to implement logic circuits. In this paper, a logic circuit based on Memristor Ratioed Logic (MRL) is proposed. Specifically, a hybrid CMOS-memristive logic family by a suitable combination of 4 memristor and a complementary inverter CMOS structure is presented. The proposed structure by having outputs of AND, OR and XOR gates of inputs at the same time, reducing the...
In this paper, a low-power voltage level shifter is proposed which is able to convert sub-threshold voltage levels of input signal to above-threshold voltage levels. The proposed circuit is based on a modified Wilson current mirror structure which employs an inverter with different gate voltages for its nMOS and pMOS transistors leading to reduce the power consumption of the circuit. Simulation results...
This paper emphasis the best efforts and technique in reduction of harmonic content of the sinusoidal waveform in ac voltage. This is done by increasing the number of steps. In general, number of bridges are determined by the formula 2N+1=Levels, where N is the number of bridges, which leads to 10 bridges. But this research makes use of 4 H-Bridges. This is achieved by making use of asymmetrical multilevel...
This paper shows how a seven level MLI can be implemented using lower number of switches using gate drive circuits built with low cost gate drive ICs such as IR2110 family. The technique uses a single dc power supply to feed all the gate drives of an inverter. This type of implementation reduces the total cost of implementation of seven-level MLI and size of driver circuits. Another important feature...
The paper deals with the implementation of a Multi-level inverter which is based on cascaded half-bridge, producing a 31 level output with high power quality. This paper primarily focuses on generating high level inverter output with optimal number of switches. Fundamental frequency switching method is adapted to trigger the MOSFETs for output voltage level control. Level generation circuit produces...
Many existing XOR-XNOR cells suffer from nonfull-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR-XNOR cell, is presented. Simulation results in 90-nm CMOS technology show that the proposed circuit has rail to rail outputs Also, we have gained 11%–51%, 2%–19% and 18%–52% improvement in delay, power consumption and power-delay product...
Array processors, and vision chips in particular, have mostly been designed from maximum processing speed point of view. However, there are applications in e.g. surveillance field, where the image content is analyzed rather rarely and where on the other hand the power consumption is of greater importance due to battery operation functionality. One of the major building block in the array processor...
RAM decoders were simulated on base the bulk CMOS 28-nm design rule. The result of a single nuclear particle impact on a MOS logical gate is a noise pulse as a single-event transient. The internal error decoder gives the main contribution to a noise sensibility of a RAM decoder. The combinational logic of error decoder can prevent all noise pulse propagating through NAND and NOR gates for the output...
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