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In this paper, we propose a novel design approach for Ripple Borrow Subtractor (RBS) to attain better energy and delay. At present portable electronic gadgets or systems are required in our day to day life with high performance and low energy. The subtractor is the most crucial part in the arithmetic operations and also used in the data processing applications. Systems with clocks produces lot of...
In this paper, a novel modified 4T Content addressable memory (CAM) cell based Master-Slave Match Line (MSML) design for memory architectures is proposed. In memory architectures, match lines (MLs) and search lines (SLs) are main source of power consumption. The Proposed Modified 4T CAM cell based MSML design which reduces delay by 74%–95% with increases total power consumption and area compared with...
This paper proposes a statistical modeling methodology of RTN (Random Telegraph Noise) gate size dependency utilizing skewed ring oscillator (RO) structures. An iterative characterization flow is developed to estimate RTN induced threshold distribution of each gate sizes of pMOSFET and nMOSFET independently. The skewed RO based test structure was fabricated in a 65 nm SOTB (Silicon On Thin Body) process...
Soft error is one of the major threats for resilient computing. Unlike SRAM soft error, which can be effectively protected by ECC, Flip-Flop soft error protection can be costly. We observe that flip-flops/latches can have asymmetric soft error rates when storing different logic values. This asymmetry can be used in conjunction with the different signal probabilities of registers in a design. In this...
Comparator is the vital building block of analog to digital converter. The need for energy efficient and high speed analog-to-digital converters is necessary for the use of dynamic regenerative comparators to improve speed and efficiency of power. Fast ADCs, such as flash ADCs, requires an energy efficient comparator with small chip area. In this work comparison is performed among the delay of single...
This brief proposes an improved XOR logic gate and a novel full adder. The presented XOR has simple structure which consists of 2 CMOS transistors and 4 memristors, and it reduces 4 CMOS transistors compared with the previous. In addition, the novel full adder consists of 7 CMOS transistors and 10 memristors. This novel full adder reduces 8 CMOS transistors and 2 memristors, which means the size of...
This paper presents a 300 MHz to 3 GHz Low-Noise Amplifier (LNA) with high HP3 and one of the smallest silicon area we could find. It is based on a single amplifier, where it is systematically optimized to achieve better results than more complex noise canceling topologies, thus, saving area and power consumption. A CMOS inverter with resistive feedback where transistors are self-biased in strong...
A new circuit technique, the reconfigurable puise generator circuit is proposed to produce a puise width inversely proportional to the spectrum power bandwidth in the Impulse Radio Ultra-Wide Band (IR-UWB) circuits. The complete circuit was based on two pulse generator blocks using Positive Pulse Generator (PPG), and Negative Pulse Generator (NPG) to compose a rectangular waveform at the output. These...
Ultra-low-voltage operation is highly demanded in a system that adopts the DVFS scheme, e.g., a portable device that sustains days-long standby with a tiny battery. Such a system usually embeds modules that have specific minimum supply voltages. Point-of-load low-dropout regulators (LDOs) are used to power these modules as per the required applications, from a global supply rail Vdd. The global Vdd...
The main building blocks used in digital signal processing and multimedia applications are the adders and multipliers. Better the performance of adder structure better will be the performance of multipliers in total aspect. Reducing power dissipation, delay and area at the circuit level is considered as one of the major factors in developing low power systems. In this we present different topologies...
Conventional analog/mixed-signal (AMS) circuits design methodology relying heavily on the use of operational amplifiers (opamps) to process signals in voltage-domain (VD) encounters severe difficulties in advanced nanometer-scale CMOS process. We present a novel scaling compatible, synthesis friendly ring voltage-controlled oscillator (VCO) based time-domain (TD) delta-sigma analog-to-digital converter...
Multilevel inverters allow to generate AC voltages with low total harmonic distortion (THD) but requires an increased number of power switches. One of the disadvantages of that is the increased probability of a fault in one of the power switches. Thus in order to improve the reliability of the converter a fast and robust fault detection scheme must be used. In this context this paper presents a new...
The paper presents SiC-based three-level T-type modules designed for a high-performance 30kVA DC/AC inverter operating at high frequency 85 kHz with low THD of the output voltage. This inverter system consists of two integrated parts. The first part is active and contains three parallel-connected three-phase T-type modules built with fast-switching SiC power transistors. The second, passive part of...
Logic elements of programmable logic integrated circuits type FPGA (field-programmable gate array), the so-called LUT (Look Up Table), calculate one logic function from generally not more than 4 variables. This limitation of Mead and Conway is connected with the length of transmission transistors chain. However, by decomposition one constructs LUT with 5, 6 and even more variables. Nevertheless, only...
In the Recent time, SRAM became a major componentfor many VLSI Chips due to big storage memory and low accesstime. Power Consumption is the major issue for design the SRAMCMOS design System on Chip. Power consumption also effects thechip design and Speed of the SRAM. In this paper, we propose 4TSRAM Cell which is able to reduce the power consumption andArea also. As we can see from the results session,...
Data retention and power consumption during the hold mode of operation of a SRAM cell is of high importance. Hence, there is a need for a cell design that improves Static Noise Margin (SNM) and consumes low static power. This paper presents a Schmitt-Trigger (ST) based Single-Ended 11T SRAM cell that uses dual-threshold CMOS technology which exhibits high read and hold SNM and consumes low power during...
This paper reviews methods to diagnose faults over the past few years and presented with the focus on comparative fault diagnosis that use on-line and non-intrusive techniques. A simulation (using MATLAB/Simulink) study has been made on input single line to ground fault and inverter base drive open fault. The speed and accuracy of the fault diagnosis requires signal analysis using Digital Signal Processors...
Multilevel inverter (MLI) is a proven technology used for control of electrical machines, grid integration of renewables and active power filtering. The recent trends show ingenious attempts to achieve maximum number of output voltage levels with minimum number of active device count and active device rating. This paper proposes a novel family of H Bridge MLI with transistor clamp to increase number...
In this paper, we demonstrate a circuit simulation study of three dimensional (3D) double gate junctionless transistor. A ring oscillator is prepared using 20 nm Junctionless transistor made inverter. Mixed mode TCAD simulation is performed for the inverter and ring oscillator circuit. Junctionless transistor well performed for 3-stage ring oscillator. This investigation proves Junctionless transistor...
Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to the ultrathin nature, good transport properties and stable crystalline structure of MoS2. However, the reported devices and circuits based on this material have low yield because of various variation sources inherent to the growth and fabrication technology...
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