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This paper proposes the design techniques of high performance current comparator which can sense a minimum change of 8 nA for 10 μA input current. The current comparator shows fast response with 0.95 ns delay for an input current difference of 0.1 μA peak-to-peak and it can work up to 500 MHz clock frequency. The use of low impedance trans-impedance stage makes it faster and the preamplifier removes...
The domino logic style is very attractive for designing high performance digital logic circuits in Very Large Scale Integrated microprocessor chips. In this paper a four bit subtractor circuit is designed using different domino logic styles and its performance is compared with one another. The simulations were performed using L=0.12μm technology along with a supply voltage VDD =1.2V. The simulation...
Pipeline Analog to Digital Converters (ADCs) are widely used in applications that require medium to high resolution at high acquisition speed. Despite of their quite simple working principles, they usually form rather complex mixed-signal blocks, particularly if digital correction and calibration are considered. As a result, pipeline converters are difficult to test and diagnose. In this paper, we...
In this paper, an inductor-less mobile radio receiver is proposed. An 8-path band pass filter is employed at the input of the receiver to provide TX leakage suppression. The receiver is designed for LTE and UMTS lower bands and tested for worst case duplex distance of 32 MHz. The filter can be programmed to trade the noise degradation for TX suppression. For 0.3 dB noise degradation, IIP2 and IIP3...
A direct readout circuit configurable for electret or MEMS digital microphones is presented. The circuit includes a transducer interface, a programmable preamplifier, a 4th order ΣΔ modulator, a bandgap reference, a clock detection circuit, and a stability recovery system. A prototype has been realized in a 0.25μm CMOS process, performing 63dBA SINAD at 1Pa, and a consumption of 470μA at 1.6V supply...
In advanced high-speed communication systems, I/O interfaces require precise impedance matching to maintain signal integrity and avoid signal reflections due to process, voltage, temperature (PVT) variations. This paper presents a power-efficient hybrid digital impedance calibration technique with short calibration time. A high-speed GDDR5 memory I/O is taken as a case study in TSMC 65nm LP technology...
Unprocessed range images acquired by some range sensing modality often show bumpy surfaces and distorted object boundaries, complicating post processing, such as 3D-registration and feature extraction. The effects are mostly caused by noise due to sensor limitations, but can be mitigated through applying image processing techniques, as for example defect pixel interpolation, bilateral temporal averaging,...
Modern day radio-telescopes need extremely sensitive receivers combined with powerful signal processing capabilities. Rapid urbanization and proliferation of communication devices has made these telescopes vulnerable to increasingly high levels of Radio Frequency Interference (RFI). This has necessitated development of algorithms for the mitigation of the effects of RFI either in real time or during...
Camera Electronics for remote sensing payloads having multi-sensors with different resolutions in terms of spatial, spectral and radiometric calls for large amount of data to be sent to data handling system of spacecraft in real-time. Sensors have multiple video ports to be processed with ≥12-bit digitization generating data at >12Mbps simultaneously. Conventional Parallel transmission followed...
Positron emission tomography (PET) is a molecular imaging technique that provides images of physiological processes inside the body. In clinical applications, PET image quality benefits from the time of flight (TOF) feature. This is based on measuring the difference in the arrival times of couples of nearly collinear photons generated during the PET exam on a detector ring with a resolution less than...
In this paper, the main noise contributors and their effect on single-shot precision are analysed. The TDC analysed here is based on the Nutt method, i.e. the TDC comprises of a clock counter combined with two interpolators, which are either time-to-voltage converters or dual-slope converters. We identify the main noise sources in a time-to-voltage converter and provide analytical estimations of measurement...
In this paper, the Cramér-Rao Lower Bound (CRLB) on the variance of time interval duration estimators is derived for synchronous Time-to-Digital (TDC) converters, based on a coarse counter, keeping into account the effect of noise affecting the TDC clock period. The model has been validated using Montecarlo analysis. By comparing the CRLB to the variance of the TDC output, also theoretically modeled...
This paper presents the design and performance of a new readout system for gaseous and silicon detectors built for the Minos nuclear physics experiment. A major constraint was to provide a multi-thousand channel, high performance readout system with low manpower effort and tight cost. This was achieved by the re-use of some earlier ASIC and front-end card (FEC) developments, the design of a new digital...
As a building block of analog-to-digital converter (ADC), comparator plays an important role, especially the case latched comparator for super-high speed ADC. The speed and performance of latched comparator mostly decide the performance of the whole ADC. In this paper, a multi-stage purely dynamic high speed latched comparator for folding and interpolating ADC is designed with Bi-CMOS 0.18um process...
The concept of a tile hadron calorimeter (HCAL) for the International Linear Collider (ILC) has been developed. A major aspect is the improvement of the jet energy resolution by measuring details of the shower development and combining them with the data of the tracking chamber (particle flow). The concept utilizes scintillating tiles that are read out by novel Silicon Photomultipliers (SiPMs) and...
Positron Emission Tomography (PET) combined with Magnetic Resonance Imaging (MRI) as a hybrid imaging modality is about to become the next-generation imaging technique in the field of molecular imaging. The integration of PET detectors into an MR-gantry enabling simultaneous acquisitions with unaffected performance of PET and MRI is challenging, as PET detectors need to be unaffected by the MR operation,...
Hardware Trojan horses (HTHs) are important threats to the trustworthiness of hardware chips. Design-forhardware-trust (DFHT) techniques are used to enhance the detectability of possible HTHs. Existing DFHT approaches are usually ad-hoc techniques. This characteristic makes them vulnerable to neutralization efforts. We study this concept by focusing on an effective available DFHT technique, namely...
Dynamic logic is well suited to implement very fine-grained pipelining for high performance functional units and has been successfully applied in commercial applications. Technology scaling and current increasing frequency targets have augmented the main problems exhibited by conventional dynamic gates topologies: larger leakage and coupling leading to higher noise susceptibility, logic design constrained...
This paper presents the design of a second order double-sampling split path Sigma Delta modulator with cross noise-coupling. The power budget for the double-sampling is reduced by using bilinear integrators, while cross noise-coupling between the two modulator loops increases the noise shaping to third order. The implementation of the noise-coupling is incorporated into the second integrator using...
A reconfigurable 65nm continuous-time low-pass ΔΣ modulator operates with a sampling frequency from 491 MHz to 1536 MHz, a signal bandwidth from 10MHz to 100 MHz, and a dynamic range of 75.4dB to 62.8 dB, respectively. Reference shuffling in the flash ADC is used to improve the linearity of the flash and DAC, while also increasing the highest sampling rate and bandwidth of the modulator.
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