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An array of Circular Transmission Line Model (CTLM) metal contacts was deposited onto the upper surface of the n-SiC/Si chips using laser micromachining as an alternative to standard photolithography technique. Thin epitaxial n-type 3C-SiC/Si chips were used since no current leakage observed in previous studies. Various laser energies were used for the CTLM pattern transfer. Low values of ρc were...
In this paper, a systematic test approach is presented for rapid detection of the defects in pre- and post-bond through-silicon vias (TSV). The cylindrical, annular, and coaxial TSVs are studied using the full-wave electromagnetic simulation. The impacts of open and pinhole defects in the pre-bond TSVs can be effectively observed in the Z-parameter variation. Then, a defect detection scheme is developed...
Perovskite solar cells are a candidate for use as space solar cells, and their radiation response is studied here for the first time. Perovskite solar cells are fabricated on a quartz substrate to prevent substrate degradation, which might otherwise affect the evaluation of radiation tolerance of the cells. As a result, superior radiation tolerance of perovskite solar cells is indicated from the comparison...
Magnetic tape drives have received significant attention for archival data storage owing to its low cost, low power consumption and large storage capacity. With the gradual shift towards cloud storage and more people relying on digital information everyday, the demand for tape drives is expected to increase steadily in the near future. Since tape drives are contact recording systems, pole tip recession...
A method for a direct extraction of individual serial resistances of MOSFET source/drain electrodes is presented. It is based on the device I–V characteristics in a saturation range measured for two device configurations inverted with respect to source and drain electrodes. A threshold voltage necessary for the saturation range modeling is determined from the non-saturation range I–V characteristics...
In this paper, the package solutions for die-to-die interconnection including fine-line substrate and ASE advance wafer level package (aWLP) have been purposed. The fin-line substrate has 3um trace width and 3um trace space on top layer with copper interconnection. For aWLP, the trace width and space of interconnection on redistribution layer (RDL) is the same with fine-line substrate. The different...
This paper presents an ideal lumped-element equivalent circuit model for on-chip monolithic transformers on silicon substrates. R, L Foster networks in a T-topology are used to capture the frequency-dependent proximity and skin effects in the transformer windings as well as substrate eddy-current effects and, hence, the complete frequency-dependent self and mutual impedances of the transformer. The...
IBM first qualified a 0.35μm generation 1000 Ω-cm high resistivity substrate (HiRES) SiGe BiCMOS technology in 2011. This technology was optimized for WiFi and cellular NPN power amplifier (PA), NPN low noise amplifier (LNA), and isolated CMOS NFET switch rf front-end-IC (FEIC) integration. It includes an optional through silicon via used as a low inductance ground path for NPN emitters. Data for...
Large scale single-crystalline graphene was achieved on copper foils with CH4 as the precursor with a sandwich method. With a PMMA-assisted method, single-crystalline graphene was transferred to the marked SiO2/Si substrate. Quantum Hall devices will be fabricated by E-beam lithography and metallization. And, quantum Hall effect will be measured.
This paper is demonstrated the effect of Ge interlayer and patterned substrate to form low resistance Ohmic contact of n-GaN. The Ge interlayer is acted as heavily n-type dopant atoms at the interface of metal and n-GaN to enhance carrier tunneling. The patterned substrate is designed to increase the annealing temperature at the interface of the metal and n-GaN. Contact resistances were derived from...
Effects of annealing on GaAs/Si bonding interfaces of III-V-on-Si hybrid tandem solar cells were investigated. Using a cross sectional transmission electron microscope, an amorphous layer was observed at the interfaces of GaAs/Si junctions that had been fabricated by the surface active bonding method. The amorphous layer vanished after the annealing at 400 °C. We also investigated the effects of the...
This paper reports novel interconnect technologies to enable a large scale ‘interposer tile’ and ‘silicon bridge’ interconnection platform. Microfabricated self-alignment structures enable high alignment accuracy between the components. Mechanically flexible interconnects (MFIs) are utilized to enable rematable electrical interconnects. Moreover, a proof of concept demonstration with interposer tiles...
This paper reviews the experimental state-of-the-art in access resistance reduction in Ge devices. Special attention is paid to the doping and thermal annealing state-of-the-art, highlighting in particular those techniques that have been applied to Si devices, but have not yet been properly optimised in Ge. We also look forward to emerging novel processes for access resistance reduction.
Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resulting in a lower wafer temperature during the etch, and a larger line width. The backside roughness of the SOI substrate must be considered in order to...
As electronic product becomes smaller and lighter with an increasing number of function↚ the demand for high density and high integration becomes stronger.! Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration;!...
A high efficiency synchronous GaN half-bridge boost converter with fast switching and low overshoot is achieved by minimizing parasitic inductance and critical damping the gate drive. A normally-off GaN-on-Si 2.4kW synchronous halfbridge Multi-Chip Module (MCM) is designed with a power-loop inductance of ∼4nH using transmission-line techniques to minimize inductance. The gate circuit inductance is...
A 2.5D three-dimensional (3D) silicon interposer with through silicon vias (TSV) was designed and fabricated. All structures are for the purpose of evaluating the design and layout, electrical testing, and to evaluate process reliability of the 2.5D interposer. Three levels are tested: chip, interposer and plastic substrate. The paper details the layout of the three levels, the principal electrical...
Wafer-scale monolayer graphene film was synthesized on Cu foils by chemical vapor deposition in a 3-in thermal furnace. Graphene film was transferred to the surface of SiO2 (300 nm)/Si substrates using a polymer-assisted method. Hall bar structures were fabricated by lithography and E-beam deposition for the electrical property measurement. Perfect symmetrical ohmic resistance distribution was achieved...
Enhancement of transistor drivability with suppressing short channel effect is a mandatory requirement for device scaling. In order to address the requirement, transistor structure transition from 2D bulk planar to SOI or 3D FinFET structures is now proceeding[1-3]. In FinFET structures, high dose tilt implantations are used in source drain extension formation. This implantations cause amorphization...
We successfully fabricated an eco-friendly Cu-Zn wetting layer for Sn-Ag-Cu (SAC) solders by electroplating in a cyanide-free solution. The reliabilities of solder joints formed on the Cu-Zn solder wetting layer were evaluated through the drop impact test and thermal cycling (T/C) test. First, boardlevel drop impact test was performed with the SAC solder joints formed on electroplated Cu or Cu-Zn...
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