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FinFET is the most promising double-gate transistor architecture to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 ??A/??m drive current respectively at 100 nA/??m leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled...
Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ??A/??m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell...
The highest electron mobility in Ge NMOS to-date, ~1.5 times the universal Si mobility, is demonstrated experimentally. Gate stack engineered with ozone-oxidation is integrated with low temperature S/D activation to fabricate Ge NMOS. Mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analyses for...
Vertical In0.53Ga0.47As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high Ion/Ioff ratio (>104). At VDS = 0.75V, a record on-current of 20??A/??m is achieved due to higher tunneling rate in narrow tunnel gap In0.53Ga0.47As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming...
In this paper, a physical model based on surface potential is presented for double gate a-Si:H TFTs. Firstly, a new model for the distribution of potential and electrical field along the bulk a-Si:H layer is proposed when both the front and back gates are biased in the positive voltages. Using this model, the front and back surface potential can be calculated from the equation groups by the iterative...
In this work we present an experimental study of the electromechanical behavior of suspended, taut, single walled carbon nanotubes (SWCNTs). A novel top-down fabrication process was developed in order to integrate the suspended SWCNTs into silicon MEMS structures fabricated using conventional micro-machining techniques. The resonant response of suspended SWCNTs under a time-varying electric field...
Fully integrated MESFETs have been shown to work on multiple commercial silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) CMOS processes without changing a step in the process flow. The unique features of the MESFET including depletion mode operation, breakdown voltages in excess of 50 V, and easy to adjust, but well controlled threshold voltages have given the designers a cost-free way to...
This work reports on gate voltage dependent source and drain series resistance and associated barrier height in modified double gate Schottky MOSFETs with dopant segregation. We show that in our devices the series resistances is significantly reduced by lowering the Schottky barrier height (SBH). The series resistance and the barrier have been extracted using an external series resistance method and...
We compare the electrical properties and interface characteristics in terms of nitrogen depth distribution and hydrogen diffusion behavior of two CVD oxide tunnel films that were nitrided by NO and N2O gas, respectively. The N2O-oxynitride shows a stronger resistance against the approach of the SiO2/Si interface by diffusing hydrogen in nuclear reaction analysis. This H diffusion behavior correlates...
We propose schemes of using graphene field effect transistors (GFET) to detect ionizing radiation. The detection is based on the high sensitivity of graphene to local change of electrical field that can result from the interaction of radiation with a semiconductor substrate in a GFET. We present preliminary modeling and experimental work to develop a prototype sensor, and discuss potential advantages...
FinFETs with 1 mum tall fins have been processed on (110) bulk silicon wafers using crystallographic etching of silicon by TMAH to form fins with nearly vertical sidewalls of an (111) surface orientation. The concept of tall, narrow fins offers more efficient use of silicon area and better performance of multi-fin devices in high-frequency analog applications. N-channel FinFETs with 1.9-nm-wide fins...
Efficient power conversion at high switching frequencies requires switching transistors with a low gate charge to limit the switching losses in addition to low specific ON resistance. We report two integrable GaAs switching pHEMTs, 14 V enhancement mode and 7 V depletion mode transistors that show much superior switching figure of merit (Ron times QG) than that of state-of-the-art silicon MOSFETs...
Twenty amp normally-off enhancement mode 4H-SiC VJFETs are demonstrated with 1.9 kV avalanche breakdown voltage and a specific on-resistance of 2.8 mOmega-cm2. The VJFETs shown near ideal subthreshold characteristics and maintain enhancement mode functionality to temperatures exceeding 175degC due to the optimized channel design with low DIBL characteristics. The low specific on-resistance enables...
Semiconductor (e.g. silicon, germanium) nanowires have gained interest as an attractive platform to fabricate field effect transistors devices because of their reduced short channel effects by comparison to planar devices. The realization of high performance nanowire devices however has been stymied primarily by large source (5) and drain (D) contact resistances. Here we report the fabrication and...
InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m ) hence high electron velocity (v). At sub-22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for high subthreshold slope and acceptably low drain induced barrier lowering (DIBL)....
The U.S. Army Research Laboratory (ARL) has been investigating silicon super gate turn-off thyristors (SGTOs) for high action pulse switching necessary for Army survivability and lethality applications. The silicon SGTO designed by Silicon Power Corporation (SPCO) was evaluated to determine its repeatable pulse current capability at a 1 ms pulse width. The initial SGTO design was a 3.5 cm2 chip rated...
A scalable, self-aligned In0.53Ga0.47As MOSFET process was developed and enhancement mode device operation was demonstrated. The 0.7 mum Lg device shows a maximum drive current of 0.14 mA/mum at Vgs=4.0 V and Vds=2.5 V. The devices have almost an order of magnitude larger drive current than our previously reported MOSFETs. The channel layer was 5 nm thick InGaAs with InAlAs bottom barrier for vertical...
We report the first demonstration of a surface channel inversion-type In0.53Ga0.47As n-MOSFET featuring gold-free palladium-germanium (PdGe) ohmic contacts and self-aligned S/D formed by silicon and phosphorus co-implantation. A gate stack comprising TaN/HfAlO/In0.53Ga0.47As is also featured. Excellent transistor output characteristics with high drain current on/off ratio of 104, high peak electron...
This paper demonstrates the integration of Al segregated NiSi/p+-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ~15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of PhiBp of NiSi on p-Si...
We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345 nA/mum and Ioff=30 nA/mum at -1 V for a 50 nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow...
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