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The effects of circuit non-idealities in a “Hogge ” -type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop...
A near-/sub-threshold programmable clock generator is proposed in this paper. The major challenge of the ultra-low voltage (ULV) circuits is that the lock-in range of the delay line is easily affected by the environmental variations. In the proposed clock generator, there is a PVT compensation unit which consists of a set of delay line and a PVT detector. The unit is responsible for adjusting the...
In this work, we propose a detection method that exploits not only the instantaneous values, but also the intrinsic dynamics of the RR series, for the detection of apnea-bradycardia episodes in preterm infants. A hidden semi-Markov model is proposed to represent and characterize the temporal evolution of observed RR series and different pre-processing methods of these series are investigated. This...
In this paper, we present a new seizure detection algorithm and the associated CMOS circuitry implementation. The proposed low-power seizure detector is a good candidate for an implantable epilepsy prosthesis. The device is designed for patient-specific seizure detection with a one variable parameter. The parameter value is extracted from a single seizure that is subsequently excluded from the validation...
To achieve natural and smooth control of prostheses, Electromyographic (EMG) signals have been investigated for decoding user intent. However, EMG signals can be easily contaminated by diverse disturbances, leading to errors in user intent recognition and threatening the safety of prostheses users. To address this problem, we propose a trust sensor interface (TSI) that contains 2 modules: (1) abnormality...
The purpose of this paper is to present a novel digital peak-current detector and the dynamic characteristics of the current mode dc-dc converter using proposed one. The proposed circuit is able to detect the peak point of the switch/reactor current in real time only by comparing two pulse trains. The circuit principle is very simple. The peak point of the switch/reactor current is realized using...
We will detail the discovery of an anomalous terrestrial source of pulsed emission which exhibits a frequency-swept signal that closely mimics the frequency-dependent delay induced by dispersion in interstellar plasma. The signals were detected through the far sidelobes of Parkes Radio Telescope, appearing in all of the 13 independently-positioned receivers installed at the dish focus. The frequency-dependent...
As process technology shrinks, the adaptive leakage power compensation scheme will become more important in realizing high-performance and low-power applications. In order to minimize total active power consumption in digital circuits, one must take into account sub-threshold leakage currents that grow exponentially as technology scales. This describes to predict how dynamic power and sub-threshold...
We consider the problem of distributed detection in wireless sensor networks. The sensors are randomly deployed according to a Poisson point process. The received power of the signal emanating form an intruding target is assumed to follow the inverse power law. We propose the real-time counting rule (rt-CR) detector to endow the system with real-time detection delay capabilities. We show that the...
In this paper, a technique to reduce the output jitter and the wide-range operation is presented. A wide-range voltage controlled delay line (WRVCDL) uses multi-band to operate on wide-range. The proposed DLL operates from 25MHz to 250MHz. An edge combiner (EC) is used to increase the output frequency range. It synthesizes frequencies from 250MHz to 2.5GHz. The output of EC will be a 50% cycle in...
A phase-based delta-sigma analog-to-digital converter (ADC) architecture with a combination voltage-controlled and digitally-controlled delay lines (VCDL-DCDL) is presented. The architecture uses this VCDL-DCDL combination as the phase-domain counterparts of an ADC-DAC in a traditional delta-sigma modulator. Simulation results of the new modulator achieve a 60.1 dB SNR, or a 9.7 bit over a 10 MHz...
In this work we present a theoretical formulation for the performance of a constant false alarm ratio (CFAR) detector for GNSS signals based on an FFT fully parallel acquisition scheme. The performance is measured in terms of receiver operating characteristic (ROC) and analytical expressions for the false alarm probability and the detection probability are derived. A detailed analysis is carried out...
Normally, research on evolutionary computation applies its algorithms to the solution or optimization of some technical or mathematical problems. But for some technical tasks, such as localization, nature seem to provides optimal solutions. This paper discusses how the barn owl auditory system can be conceptually realized on a digital system, such as a field-programmable gate array. This adapted system...
A protection algorithm for a wind turbine generator (WTG) operating in a large wind farm is described in this paper. To minimize the outage section, the protection should operate instantaneously for an internal fault or a connected power collection feeder fault, whilst remaining inoperative for an internal fault on a parallel WTG connected to the same feeder or an adjacent feeder fault. In addition,...
Energy detectors (ED) and transmitted reference (TR) systems are known as promising candidates for noncoherent UWB receivers. One way of non-coherent communication, is to use a transmitted reference (TR) pulse for detection. In conventional TR, the reference pulse and data bearing pulse are multiplexed in time domain. In frequency shifted reference (FSR) method, these pulses are multiplexed in the...
Opportunistic Dynamic Spectrum Access (DSA) systems are emerging as a key to enable the Department of Defense (DoD) to meet its technology requirements for access to the electromagnetic spectrum. One of the main goals of DSA is to protect incumbent spectrum users from interference that could be caused by DSA emitters. One of the ways to accomplish this is through spectrum sensing as means to enable...
Successful spectrum sharing in a cognitive radio network depends on the correct and quick detection of primary activity. Cooperative spectrum sensing is therefore suggested to enhance the reliability of such detection. However, it renders another significant problem of increased detection delay and traffic burden. Moreover, efficient schemes for multi-sensor data fusion should be designed. In this...
This paper describes the architecture and design of high-speed clock recovery circuit for burst-mode applications. Since the proposed circuit is non-PLL-type and designed in fully digital style, it can provide faster acquisition time, better scalability and portability compared to PLL-type or analog style clock recovery circuits. The proposed circuit recovers output clock for every transition of input...
In this paper, a new low-jitter dual-loop delay locked loop (DLL) with multi digitally controlled delay lines (DCDLs) is proposed. With this proposal, a limitation on unit delay amount is drastically reduced; hence the maximum frequency that a dual-loop DLL supports can be easily expanded into GHz range. Also, the invalidation system employed in the reference delay loop helps reduce the jitter in...
In this paper, a CMOS peak detector is proposed. The proposed peak detection is based on signal's slope variation and it can be easily exploited for positive as well as negative peak detection. Besides it can also be used for multiple peak detection without needing resetting operation, making the circuit implementation quite simple. A switched-capacitor-based (SC-based) implementation is given along...
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