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The effect of aging has become an important reliability concern in modern CMOS technology. NBTI and PBTI are known to bring about an increase in threshold voltage of the PMOS and NMOS respectively. This paper studies the effect of NBTI and PBTI on different flip-flop circuits with key parameters such as setup time, hold time, clock to output delay and data to output delay. The results in a predictive...
The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed,...
This paper proposes a tool set for the design of asynchronous circuits with bundled-data implementation. Using the proposed tool set with commercial CAD tools, asynchronous circuits with bundled-data implementation can be designed easily. Through the experiments, this paper evaluates synthesized circuits using the proposed tool set in terms of area, performance, power consumption, and energy consumption...
The pre-silicon 22/20nm LSTP models we generated are available on-line1 and can be used for fair bulk vs. FD SOI benchmarks. The proposed modeling methodology unified for bulk and FD SOI can further be used to generate models for LOP process flavor and/or 16nm CMOS node.
An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter...
A mixed-mode simulation framework is presented to study the AC performance of a 20nm bulk CMOS technology with respect to various options for contact design at the middle-of-line design level. These simulations combine the predictive capabilities of a calibrated two-dimensional TCAD model for a MOSFET with three-dimensional simulations for the layout dependent parasitic capacitances to extract the...
In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-micron (UDSM) CMOS inverter, NAND2 & NOR2 based on nth power law of MOSFET model when the channel length is of the order of less than or equal to 90nm. We have taken all the parameters from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts...
The paper introduces a new way for teaching of delay insensitive asynchronous logic circuits. The studies start on high level models, which are VHDL implementations of Dennis-type static dataflow systems. Investigating the operation of the concurrent processes of these models, the main elements of the delay insensitive systems can be derived. Introducing constant weight ‘m-of-n’ codes immediately...
This paper presents a compact model implemented in Verilog-A for PD SOI sub-micron MOSFETs, which allows for describing the Single Events Effects (SEE) produced by heavy ions. This Verilog-A module can be coupled with Spice simulator in order to have faster (time-efficient) circuit simulations with good agreement. Due to the physical aspects considered in the model, better flexibility than the standard...
Packet scheduling algorithms are viewed as one of the key mechanisms for increasing the diversity order, robustness and effectiveness of a wireless multi-user communication systems. Traditional packet scheduling algorithms are designed to save energy at the Base-station(BS) in downlink by exploiting tradeoffs between spectral efficiency, delay and energy while at the same time meeting the QoS requirements...
We introduce a novel methodology for identifying worst-case test vectors for sequential circuits in ASIC devices exposed to total dose. Testing of sequential circuits requires the use of sequence of test vectors. Those test vectors we generated using cell-level fault models for failures induced by total dose. In this paper we focused on three types of failures: logic, leakage current, and delay failures...
The continuous trend to decrease the cost-per-function and to increase the quality of integrated circuits amplifies the test challenges. Overall low production cost can be achieved only by considering the test area overhead, the test application time and the test quality. The fulfillment of these requirements is possible by application of short tests, use of low-overhead design-for-testability methods/standards...
This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS'85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental...
This paper presents a scalable asynchronous distributed control network. The control circuit allows for true asynchronous operation of all digital resources and as a result of its scalable distributed topology allows unlimited resource sharing. We start with the description of a data flow graph, and using traditional scheduling algorithms, generate an asynchronous distributed control network and the...
We present a new model order reduction technique for electrically large systems with delay elements, which can be modeled by means of neutral delayed differential equations. An adaptive multipoint expansion and model order reduction of equivalent first order systems are combined in the new proposed method that preserves the neutral delayed differential formulation. An adaptive algorithm to select...
The effects of circuit non-idealities in a “Hogge ” -type phase detector are examined. Using a behavioral model for each circuit block, it is shown that various circuit non-idealities introduce static phase offset in the phase detector, reduce the monotonic range of its transfer characteristics and eventually degrade the capture range and jitter tolerance of the clock and data recovery (CDR) loop...
This paper presents a don't-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don't-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0% of total dynamic power. An algorithm for glitch reduction is then presented, which takes advantage of don't-cares in the circuit by setting their values based on the circuit's...
Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for checking. Comparing the model WLDDs, the experiments show that the WGL...
The Carbon NanoTube Field Effect Transistor (CNTFET) is a promising device to supersede the MOSFET at the end of the technology roadmap of CMOS. One of the likely defect types that may occur in the manufacturing process is that the diameter of a CNT could be changed and not all CNTs are deposited. This paper deals with the degradation scenario in which different CNT parameters (the diameter, the number,...
As semiconductor manufacturing has entered into nanoscale era, performance degradation due to Negative Bias Temperature Instability (NBTI) became one of the major threats to circuits reliability. In this paper, we present an NBTI gate delay model and a technique to mitigate its impact on circuit delays. First, we model NBTI impact on a gate while considering both the degradation of its own transistors...
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