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The paper introduces a new way for teaching of delay insensitive asynchronous logic circuits. The studies start on high level models, which are VHDL implementations of Dennis-type static dataflow systems. Investigating the operation of the concurrent processes of these models, the main elements of the delay insensitive systems can be derived. Introducing constant weight ‘m-of-n’ codes immediately...
The paper considers a railway timetable related problem in a simplified form, generated by the delay of one or several incoming trains at a given station. Usually there are connecting trains in the timetable, especially in up to date periodic timetables and thus incoming delays might indicate the necessity of introducing a delay with connecting outgoing trains. A hierarchical fuzzy rule base is applied...
The handling of traffic conflicts of trains is rather complicated if full dynamic models are used. Often it is senseless to take into consideration all details of the motion equations and environmental parameters especially as the main parameters, like maximum speed of the trains involved are not exactly known. Also, a large number of noise type variables are always available. The paper proposes the...
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