The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper proposes Progressive Mixing Injection Locked Frequency Divider (PMILFD) technique that enhances the locking range for higher division ratios. The wide locking range is achieved through the use of progressive mixing approach contrary to the conventional method that uses direct mixing to generate the injection signal. This allows for the use of lower and much stronger harmonics in the mixing...
Design objectives of robustness and low-power usually do not go hand in hand with the test objectives of maximum test coverage and minimum test cost. Low power robust design techniques such as dual-Vth, dual-VDD, or adaptive body biasing have negative impact on the associated test cost. Similarly, test techniques like enhanced scan have large overhead in terms of area and power. In this paper, we...
An analysis of XOR gate designed using Gate Diffusion Input (GDI) technique is presented in this work. Comparative investigations are also carried out for XOR gates designed using conventional, low power as well as GDI techniques. SPICE simulations verify the results. The analysis shows that at 100MHz, circuit designed using GDI technique consumes 73.79%, 73.61%, and 46.64% less power compared to...
The insatiable demand for increased energy-efficient communication bandwidth has led to the widespread adoption of serial-links. Serializer/Deserializer (SerDes) architectures have seen considerable use in both inter — and intra-chip communication of high-performance computing platforms and embedded systems. Serializers translate m-bit parallel data into a serial stream of increased data rate. Bus...
This paper presents a 65–85 GHz 5-bit passive phase shifter at the desired frequency of 77 GHz, using CMOS switches available in the 0.13 µm SiGe BiCMOS process. The phase shifter is based on a low-pass π-network and CMOS passive transistors. The RMS phase error, the insertion loss and the VSWR is less than 3.5°, −20 dB and 2 at 77 GHz respectively, so it is possible to precede this design with a...
Reducing power consumption is a major concern in mobile applications, since they are battery operated and require high performance. In this paper, a novel technique to reduce the power consumed by embedded SRAM memory is introduced. The proposed method is an on-chip circuit to measure the optimal data retention voltage (DRV) of the SRAM array. The implemented DRV computing circuit consists of a built-in-self-test...
The effect of aging has become an important reliability concern in modern CMOS technology. NBTI and PBTI are known to bring about an increase in threshold voltage of the PMOS and NMOS respectively. This paper studies the effect of NBTI and PBTI on different flip-flop circuits with key parameters such as setup time, hold time, clock to output delay and data to output delay. The results in a predictive...
This paper presents a design of an UWB PPM — Pulse Position Modulation transmitter based on a 1.8V, 0.18μm CMOS technology. We propose a pulse generator using modified Nand gate as a Phase Detector (PD) with an effective phase difference of 73ps. At the PD output an extra derivative circuitry exists. The whole circuit has been simulated using LTSpice and the results had demonstrated the circuit capability...
The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed,...
In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining...
A reduced power delay element for the temporal hardening of sequential digital circuits is presented. The delay element single event transient (SET) tolerance is demonstrated by simulations using it in a radiation hardened by design (RHBD) master slave flip-flop (FF). Using the proposed delay element saves up to 25% total FF power at 50% activity factor. The delay element incorporates redundancy to...
This paper proposes methods for taking advantage during voltage-based production test of the capability to control well and substrate (body) biases separately from the chip's VDD and GND. Such control is a by-product of a low-power design strategy that allows parts or all of the chip to go into low-power reduced-leakage states. The proposed test methods use body bias manipulation to increase or decrease...
Technology scaling is in the era where the chip performance is constrained by its power dissipation. Although the power limits vary with the application domain, they dictate the choice of technology, architecture, and implementation techniques that trade off performance for power savings. Energy-efficient design is often achieved for designs that are sensitive to technology and design parameters....
This paper presents a new architecture for a overcurrent detection system, dedicated to fully integrated class-D audio amplifiers, that uses half the comparators than conventional architectures. A detailed implementation for a 1-W bridge-tied load (BTL) class-D amplifier, on a 0.18 µm CMOS technology is presented, showing a reduction of 28.8% in current consumption and 23.5% in silicon area, when...
Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. The main drawbacks are performance degradation due to the exponentially reduced driving current, and the effect of increased sensitivity to process variation. To obtain energy savings while reducing performance degradation, we propose the design of a robust sub-threshold library and post-silicon...
Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage...
Flip-flop metastability is becoming an important consideration for designing reliable synchronous and asynchronous systems, especially in the sub-threshold region where it degrades exponentially with the reduction in supply voltage. In this paper, detailed analysis is given on the design of metastable-hardened flip-flops in the sub-threshold region. Proper transistor sizing using either transconductance...
Reducing the supply voltage is by far the most widely used low-power technique, as reducing dynamic power quadratically and leakage power linearly, while sacrificing on performances. A similar but less explored route is to reduce and/or limit currents (instead of reducing voltages), e.g., through transistor sizing. This paper details a comparison of a reverse-sized CMOS scheme (which reduces currents),...
Switched capacitor circuits have become a popular method for implementing mixed signal blocks in standard CMOS technologies. Non-Overlapping Clock (NOC) generator is a key building block of switched capacitor circuits. Standard NOC circuits use simple inverters to realize delays. For high to moderate frequencies, the number of inverters required is nominal. But for low frequency applications like...
In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency. In...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.