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Mobile devices such as smartphones have two major restrictions from the standpoint of design: thermal dissipation and the supply of battery power. Thermal dissipation restricts power consumption of AP (Application Processor), which additionally limits computational performance. Battery usage time is also determined by power consumption of the mobile device. Due to these reasons, power management to...
Future society requires networking of efficient portable, wearable, implantable IT/electronics and sensors for mobile, healthcare, smart grid and robot services. Power of small terminals operated by batteries or energy harvesting means, obviously need to be reduced. Power of data centers with much more processing capability and storage capacity compared to those now, also need to be reduced. Challenge...
An SoC integrating both an IEEE 802.11n Wireless LAN (WLAN) and a high quality codec is implemented using 90nm CMOS technology for wireless connectivity between full HD video-supporting devices. The WLAN operates with up to 270-Mbps data rates using 2×3 MIMO technologies and the codec supports up to 1080P 60Hz resolution with 30-bit RGB color format. The system achieves total 18ms latency, which enables...
This paper describes the Second Generation Intel® Core™ processor, a 32nm monolithic die integrating four IA cores, a processor graphics and a memory controller. The die was designed for high performance but without compromising the part power consumption or the part and system cost. To achieve these targets a modular design methodology was devised, this methodology allows fast configuration of the...
This paper describes the design and LSI implementation of a dynamic SIMD/MIMD mode switching processor core (the XC core) for embedded real-time image recognition systems. The XC core supports both a highly parallel SIMD and a medium parallel MIMD architecture, which are suitable for exploiting the large amount of data-level and task-level parallelisms respectively that exist in most image recognition...
This paper presents embedded use DC-DC boost converters for battery operating micro-computers. Pulse frequency modulation (PFM) is employed for fast response. A new control method is applied to improve the efficiency by regulating the inductor current optimally from both of input voltage and load current. A synchronous rectifier converter fabricated by a 180nm CMOS technology achieves the efficiency...
In this paper, we explore the effectiveness of various solutions that can be applied to improve the performance of SE signaling at small incremental cost to the system. Specifically, we examine solutions for mitigating the impact of crosstalk, supply noise, and inter-symbol interference (ISI) to enable reliable communication over a graphics memory channel at 12.8-Gbps. We further compare measured...
Digital “assist” circuits can improve the efficiency of traditionally analog circuit blocks, especially as technologies scale to the detriment of analog blocks. We apply some of these techniques to a 10 Gbps optical reciever, and demonstrate 395 fJ/b energy efficiency. Digital calibration blocks wrapped around a simple analog core enabled offset compensation, TIA biasing, and DLL re-timing, and cost...
A low startup-voltage and fast startup dual-mode boost converter for energy harvesting applications is developed in 65-nm CMOS. Comparing with the previous work [6], the startup-time, the minimum startup voltage, and the program time are greatly improved. (1) A startup by the boost converter instead of a charge pump reduced the startup-time to 4.8ms which is 1/56 of [6] and the shortest to date. (2)...
A fast transient-response digital low-dropout (LDO) voltage regulator comprising only low-voltage MOS transistors was developed. The input voltage can be higher than the withstand voltage of the low-voltage MOS transistors by the proposed withstand-voltage relaxation scheme. The switching frequency of 1 GHz can be achieved using small-dimension low-voltage power-MOS transistors. The LDO occupies only...
A new Ripple Current Controlled Boost Converter with capacitor-free LDO as a power IC for digital driving AMOLED display is presented to achieve high stability for load variation. And a flying capacitor as well as an inductor is adopted as another energy transfer medium to increase the converter efficiency. The proposed chip is implemented in a 0.35-μm power BCD process. Transient dip voltage of the...
Conventionally for wide workload range applications, to keep good stability and high efficiency, a switching converter with multi-mode operation is necessary. With the advanced digital signal processing, this work presents an asynchronous digital controller with dynamic power saving to achieve high power efficiency. The regulation is based on the constant on-time technique, while an adaptive resolution...
In order to elevate an input voltage of less than 1-V to an output voltage of from several volts to 10-V while also realizing a large output-current capability, a wide feedback-loop frequency bandwidth under a high duty-ratio condition and a high power efficiency, we developed a MOS current-mode boost DC-DC converter which utilizes the quadratic compensation slope with the output voltage dependency...
A switching regulator with quasi-V2 adaptive on-time (AOT) control, that provides a fast load transient response is proposed. A feed-forward path network allows the proposed switching regulator to achieve a fast transient response and stable operation without requiring an output capacitor with a large equivalent series resistance. The proposed AOT controller makes the switching frequency pseudo fixed...
A Time-Interleaved (TI) pipelined-SAR ADC with on-chip offset cancellation technique is presented. The design reuses the SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time. A 6 bit capacitive DAC is built as a flip-around MDAC for low inter-stage gain implementation. The capacitive attenuation solutions in both 1st and 2nd DACs minimize the power dissipation...
The design of a Ternary Successive Approximation ADC (TSAR) with decision time quantization is proposed. The TSAR examines the transient information of the typical SAR comparator to provide full half-bit redundancy, an increased monotonicity switching algorithm, speed enhancements without inherent metastability, residue shaping effects, and stage skipping. A prototype is fabricated in 0.13μm CMOS...
This paper presents a new subrange analog-to-digital converter (ADC): a binary-search coarse ADC + a SAR fine ADC. The binary-search ADC improves conversion speed and gives coarse capacitors longer settling time. This ADC uses an RC hybrid DAC to reduce the unit capacitor count by 2. The rotation function of coarse capacitors enhances capacitor array linearity. The prototype in 90-nm CMOS only occupies...
This paper presents a topology to improve the system linearity and reduce the complexity of high-speed binary-search ADCs. The proposed topology, when compared with previous binary-search ADC architectures, further reduces the number of comparators from 2N-1 to N for N-bit precision, the comparator structure is simplified, and it can avoid both the signal dependent offsets and the kickback noise....
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