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The 3N encoding process can simply add the input data N to its 1-bit left-shifted value 2N using the combinational digital circuits, such as ripple carry adder (RCA) or carry look-ahead adder (CLA). This paper presents an efficient algorithm and its hardware implementation. Results show that the proposed RCA-like 16-bit encoder achieves 25% less in hardware cost and 50% faster in speed performance...
In this paper we present the design of an on-lineadder dealing with two RBCD numbers. This basic elementis intended to be be used in any on-line system in which theaddition is involved. We obtain the on-line adder by serializa-tion of a recent parallel RBCD adder with minimum latency.To reduce the cycle time a pipelined version is proposed. Todeal with data stream the throughput has been reduced toits...
A technique, based on the residue number system (RNS) with diminished-1 encoded channel, has being used for implementing a finite impulse response (FIR) digital filter. The proposed RNS architecture of the filter consists of three main blocks: forward and reverse converter and arithmetic processor for each channel. Architecture for residue to binary (reverse) convertor with diminished-1 encoded channel...
As system sizes grow and devices become more sensitive to faults, adder protection may be necessary to achieve system error-rate bounds. This study investigates a novel fault detection scheme for fast adders, long residue checking (LRC), which has substantive advantages over all previous separable approaches. Long residues are found to provide a ~10% reduction in complexity and ~25% reduction in power...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
This paper presents a novel approach to perform modular arithmetic addition and subtraction using base-1 thermometer code data format for operands corresponding to the residues of the same modulus. Two n-bit thermometer code operands are first concatenated and logically shifted to produce a normalized 2n-bit thermometer code intermediate sum. Modulo operation is then applied to this 2n-bit intermediate...
With the advent of deep sub micron era, design closure is becoming harder to achieve. In high-level synthesis, slack is a very effective means of tolerating uncertainties. Thus, several research efforts have been paid to study the slack-driven high-level synthesis problem. However, previous works cannot actually maximize the total slack value, because they are limited to either the operation scheduling...
A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit...
In this paper, a new high-speed full adder cell called “Floating full adder” has been proposed. This design offers a full adder with 8 transistors which its internal nodes are not directly connected to the ground. Simulations have been performed by Hspice software based on 90nm CMOS model, BSIM4 (level 54) version 4.4. Simulation results show that suggested circuit has maximum propagation delay equal...
A low power, low complexity full adder design based on degenerate pass transistor logic (PTL) is described. The design kernel is a logically degenerate 5-transistor XOR-XNOR module supporting complementary outputs. In spite of the logic deficiency, this module functions properly in the context of full adder applications. The threshold loss problem common in most PTL designs can be alleviated due to...
Prefix computation is one of the fundamental problems that can be used in many applications such as fast adders. Most proposed parallel prefix circuits assume that the circuit is of the same width as the input size. In this paper, we present a class of parallel prefix circuits that perform well when the input size, n, is more than the width of the circuit, m. That is, the proposed circuit is an almost...
Decimal arithmetic has gained high impact on the overall performance of today's financial and commercial applications. Decimal additions and multiplication are the main decimal operations used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FPGAs provide an efficient hardware platform...
In this paper a 16-bit radix-4 pipelined divider implemented in a modified version of D3L family structure is presented. Performance of the circuit is evaluated and presented at different simulation corners. The results show that, compared with its dynamic version, the proposed circuit has lower power consumption and higher speed. Latency of the divider is equal to 10 half clock cycles. The circuit...
In this paper, we present an efficient and modified lifting based architecture for 2-D lifting-based DWT in JPEG2000 applications. The Proposed 2-D DWT architecture is composed of one 1-D DWT cores and transposing register array. The proposed 1-D DWT core consumes two input data and produces two output coefficients per cycle, and its critical path takes one multiplier delay only. The Proposed architecture...
This paper presents a new approach for the high performance and hardware efficient design of coordinate rotation digital computer (CORDIC) processor structure. The proposed design approach completely eliminates the ROM requirement of constant arctangent values. Furthermore, efficient designs of carry look ahead adders (CLAs), exploiting one input as constant, in the angle adder/subtractor datapath...
Decimal multiplication is one of the most frequently used operations in financial, scientific, commercial and internet-based applications. This paper presents an efficient implementation of a fully pipelined decimal multiplier designed with Carry Save Addition and coded into a reduced group of BCD-4221. This design is based on multiplier operands recoded in Signed-Digit radix-10, a simplified partial...
This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper...
In this work we introduce a hybrid CLA-Ripple Power-aware adder (or simply HICPA) for high performance processors. HICPA is a multi-component adder that saves power by avoiding aggressive usage of the Carry Look-Ahead adder for add operations using small operands. Instead, for small size operands, HICPA uses a small and power efficient Ripple Adder. We evaluate HICPA using a subset of SPEC'2K benchmarks...
Reversible logic gates are in demand for the upcoming future computing technologies. Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design. The paper proposes the design of full Adder/Subtractor circuit using fault tolerant reversible logic gates. The design can work singly as a reversible Full Adder/Subtractor unit. It is...
This paper proposes a novel simultaneous allocation and binding method in high-level synthesis, which minimizes the circuit area including multiplexers (MUXs) under a clock constraint. Most existing works on binding minimize MUXs under given allocation by minimizing the number of interconnections, but do not care where the MUXs would be inserted in a circuit. As a result, they cannot guarantee the...
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