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We present a digital phase interpolator (PI) design for 65nm CMOS that avoids conventional analog structures, accurately achieves 2-bits phase resolution across a range of rise time and input delays from trise: 48ps → 200ps using a ratio trise/tdelay of at least 1 or greater. Increased accuracy is available for certain rise times using ratios increasing between 1 and 10 as verified by simulations...
A clock-deskewing circuit (CDC) using a dual delay-locked-loop technique is presented. The CDC can synchronize the clocks for a chip-to-chip system without delay measurements and dummy delay elements. Simulated in a 0.18µm CMOS technology, the maximum operating frequency is 1.5 GHz and the cycle-to-cycle clock jitter is 7.74 ps. Total power dissipation of the CDC is 56mW under a 1.8-V supply.
This paper discusses about the design of a novel and fast 4-2 compressor. To enhance the speed performance, some changes are performed in the truth table of conventional 4-2 compressor which leaded to reduction of gate level delay to 2 XOR logic gates plus 1 transistor for all parameters. Because of similar paths, there will be no need for extra buffers in low latency paths to equalize the delays...
A novel high speed Carry Look Ahead Adder (CLA) is presented. The proposed CLA is implemented using Dual Mode Logic (DML) methodology, as recently introduced by our group. DML allows dynamic switching between static and dynamic modes of operation. In static mode, the DML gates feature very low power dissipation with moderate performance, while in dynamic mode they achieve higher performance, albeit...
With CMOS technology shrinking to nanoscale regime, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for...
As the complementary metal oxide semiconductor (CMOS) scaling become harder, researchers have been trying to improve field programmable gate array (FPGA) performance by utilizing nonvolatile memory devices. This paper reports on a novel FPGA architecture where nonvolatile memory devices are used as nonvolatile reconfigurable switches (NRSs). It has found that resistive change memory (RCM) can be utilized...
In this paper, a new high-speed full adder cell called “Floating full adder” has been proposed. This design offers a full adder with 8 transistors which its internal nodes are not directly connected to the ground. Simulations have been performed by Hspice software based on 90nm CMOS model, BSIM4 (level 54) version 4.4. Simulation results show that suggested circuit has maximum propagation delay equal...
A two-dimensional (2D) space-time (ST) delay operator D2DST [·] and a novel discrete-space-continuous-time (DSCT) CMOS VLSI implementation at radio frequency (RF) is proposed. The proposed delay operator is able to delay 2D ST antenna array signals along space and time and can be used as a building block in 2D ST array processing algorithms. A 2D non-separable DSCT transfer function (TF), ΦApp (zx...
Historically, circuits that operate in a high-temperature region could cause an increase in the total delay (td) especially in the process technology prior to the 90nm node. This was because both interconnects and transistors were slowing down as the temperature rose. However, for transistors with the 90nm process technology and beyond, this phenomena has started to change. In particular, the threshold...
A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common...
FinFET devices with superior ability in controlling leakage and minimizing short channel effects are anticipated to replace CMOS devices in the near future. This paper presents a design of voltage sensor in 32 nm FinFET. Based on the operation of a p-type FinFET in low-power mode and independent-gate mode, a new technique for designing a controllable delay element (CDE) with high linearity is presented...
Technology scaling introduces many sources of variability and uncertainty that are difficult to model and predict [3]. The result of these uncertainties is a degradation in our ability to predict the performance of fabricated chips, i.e., a lack of model-to-hardware matching. The prediction of circuit performance is the result of a complex hierarchy of models starting at the basic MOSFET device model...
In Ultra Deep Sub Micron technology nodes, particularly 45nm and below, multiple power supplies are needed to achieve optimum performance. In such SoC's, level shifters play an important role in translating the signals from one voltage level to another. The conventional level shifters suffer from the contention between the pull up and pull down transistors which leads to the increase in delay and...
A capacitively-divided, injection-locked, ring oscillator is proposed that decreases dynamic power consumption by reducing voltage swing. A feedforward capacitor is placed in series with the load capacitance, effectively AC coupling each inverter stage to the next stage. Simulations are performed using digital programmability of the capacitor weights of both the feedforward and load capacitors, showing...
● Ambient electronics needs several new features including ultra-low power design and large-area electronics. ● Watch out for VDDmin in using ultra-low voltage domain: one bad transistor kills a chip. Escape from using small sized Tr's. ● New types of switch are emerging: ➔ Steeper-S switch to break energy efficiency barrier ➔ Printable switches for large-area electronics
Closing the THz gap would lead to a tremendous of advancement in a wide range of applications such as biomedical imaging, security, and material inspection. The gap refers to the lack of devices for the manipulation of THz radiation as compared to its microwave and optical counterparts. Plasmonic devices based on semiconductors rather than metals allow the realization of efficient and small scale...
A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has...
This paper presents two adder compressors architectures addressing high-speed and low power. Adder compressors are used to implement arithmetic circuits such as multipliers and digital signal processing units like the Fast Fourier Transform (FTT). To address the objective of high-speed and low power, it is well known that optimization efforts should be applied in all abstraction levels. In this paper...
Narrow-band phased-array transmitters provide an efficient way of obtaining higher power through spatial combining and achieving higher transmitter EIRP. They also provide beamforming and beam-steering capabilities [1]. However, the commonly used phase shifter or LO phase-shifting techniques at RF become less attractive for 3-to-5GHz UWB due to their lossy, bulky and narrowband characteristics. On...
Integration of radios in SoCs along with digital baseband and application processors is desirable for cost and form-factor reasons. Digital processors are typically implemented in the latest CMOS process to take advantage of the increased density and performance afforded by CMOS scaling. Integration of traditional RF circuits, however, requires accurate RF and passive models that typically lag behind...
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