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This paper presents a construction of dual-edge-triggered flip-flops (DET-FFs) with timing error detection capability. The proposed FF is based on a conventional DET-FF and a conventional timing error detection method. While the conventional timing error detection uses a transition detector with the area of large, the proposed FF uses internal signals in a DET-FF as an alternative of the transition...
A novel method is proposed to enhance SET propagation probability and it is shown how it can assist the hardening process. This paper provides a method to determine a set of patterns that must be applied at the inputs to determine propagation characteristics of the SET that are meaningful for hardening purposes. The impact of the proposed method is experimentally verified on the ISCAS and ITC benchmarks.
As the number of ECUs in an automobile steadily increases, the demand for ever more ECUs connected to the Controller Area Network (CAN) also rises significantly. However, the number of connectable ECUs in a linear passive star CAN is restricted because of the ringing phenomenon in communication signals. In this paper, we propose a ringing suppression circuit activated on high level ringing voltages...
Recently new Residue Number Systems (RNS) moduli sets have been proposed in order to increase the dynamic range and reduce the width of channels, therefore, reducing the processing time and further exploiting the carry-free characteristic of the modular arithmetic. In this paper we propose improved units for addition, subtraction, and multiplication in RNS for modulo {2^n+-k}. With this work, the...
The QRS detection is the entry point for almost all the ECG applications. This paper presents a new simple and efficient FPGA-Based implementation of the well-known Pan and Tompkins QRS detection algorithm. The design is implemented using Xilinx design tool, System Generator for DSP. In the authors' view, the specific features, that is simplicity, efficiency and authenticity, of the proposed model...
This paper presents a hybrid switch that parallels a power MOSFET and an IGBT as the main switch of a zero-voltage switching inverter. The combination features the MOSFET conducting in the low current region and the IGBT conducting in the high current region, and the soft switching avoids the reverse recovery problem during the device turn-on. A custom hybrid switch module has been developed for a...
With deeply scaled CMOS technology, Bias Temperature Instability (BTI) has become one of the most critical degradation mechanisms impacting the device reliability. In this paper, we present the BTI evaluation of a single inverter gate covering both the PMOS and NMOS degradations in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic...
A Monte Carlo based approach capable of identifying the probability distributions that describe the delay of every sensitizable path in a path implicit manner is proposed. It is shown experimentally that the statistical information for all paths is generated as fast as the traditional Monte Carlo simulation that identifies the probability density function for the circuit delay.
In this paper, we present a timing-driven test generator to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path,...
In this paper, we present the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access time, retention time, and static power consumption of the cell when it is exposed to the effects of process and environmental variations. Process variations are extracted from the ITRS...
As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing...
In emergency and rescue operations, wireless mesh networks are attracting increased attention as a high-performance and low-cost solution for ubiquitous network access. In this paper, we evaluate the novel secure mesh route discovery protocol PASER, which has been designed to address the mesh network security in such critical environments. The protocol aims to set up reliable ad-hoc routes between...
With ever growing demands of mobile devices, low power consumption has become essential for VLSI circuits. Since standard cell libraries are typically used in many parts of VLSI circuits, their performance has a strong impact on realizing high speed and low power VLSI circuits. One of the most promising approaches for reducing the power consumption of the circuit is lowering the supply voltage. However...
The Stored Unibit Transfer (SUT) encoding has been recently proposed as a redundant high-radix encoding for each of the channels of a Residue Number System (RNS) that can improve the efficiency of Binary Signed Digit (BSD)-encoded RNS. However, a residue-to-binary (reverse) converter for it has not yet been reported in the open literature. In this paper we introduce SUT-RNS reverse converters for...
This paper presents a methodology to model and analyze the functional behavior of logic circuits under timing variations. In the framework, first a Time Accurate Model (TAM) of the circuit is constructed. The TAM represents the behavior of the circuit in the functional domain under a discrete time model. Afterwards, Variation Logic is inserted to apply the timing variations. Moreover, the circuit...
A new scheduling module, the Selective Early Detection (SED) mechanism is proposed in this paper. An experimental evaluation in order to demonstrate how this algorithm succeeds in enhancing the quality, improving the performance and easing the deployment of a production level service is carried out. SED algorithm is useful in controlling the Actual average queue size, and hence the queuing delay,...
Based on GPRS Time Based Charging Gateway (TBCG) in one communication operator, the Paper analyses processing bottleneck of this module. It caused system inefficient and inconsistency of the user order data between TBCG and BOSS (Business Operation Support System). On the basis of current GPRS Charge Detail Record (CDR) processing procedure in the BOSS, it adds a new CDR processing module of GPRS...
ZigBee wireless technology is a global standard of short-range and low-data-rate for wireless sensor networks. To reduce the redundant overhead and to conserve nodes' energy in energy-constrained and multi-PAN ZigBee networks, we propose in this paper a cross-layer energy-balanced inter-PAN routing algorithm (CEIPR). The proposed algorithm has three key functionalities: (1) establishes the multipath...
In combinational circuit skewed gates are very attractive along the critical paths to improve delay as well as leakage current of certain design. Conventional static un-skew CMOS network will not favor the outputs to switch in certain direction like high or low. However, skewed logic gates in static CMOS network can favor a certain direction because each gate is guaranteed to solely make only a pull-up...
Due to continuous technology scaling, the nodal capacitances reduction and power supply voltage lowering result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. CMOS circuits operating under sub-threshold voltage region are more susceptible than ever to externally induced radiation that is likely to bring about the occurrence of soft errors. Therefore,...
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