The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We propose a three-dimensional polarization splitter and rotator with high fabrication tolerance and CMOS BEOL compatibility, achieving a high TE-TE transmission and TM-TE conversion efficiency of −0.21dB and −0.63dB at 1310nm, respectively.
High frequency wine-glass mode bulk MEMS resonators actuated by means of capacitive transduction have been fabricated by using solid-gaps based on polyvinylidenefluoride-trifluoroethylene (PVDF-TrFE). The fabrication process flow of patterned PVDF-TrFE gaps applied in RF MEMS is presented for the first time. Measurements of the polarization of the material and the frequency and voltage dependence...
A corporate feed slotted waveguide array antenna with broadband characteristics in term of gain in the 350 GHz band is achieved by measurement for the first time. The etching accuracy for thin laminated plates of the diffusion bonding process with conventional chemical etching is limited to ±20μm. This limits the use of this process for antenna fabrication in the submillimeter wave band where the...
In this talk we will discuss fabrication and device aspects of IBMs work on III–V Tunnel FETs. Since our focus is on the monolithic integration of III–V on Si, we will show our recently developed Template Assisted Selective Epitaxy (TASE) technology and its application to both TFETs as well as other electronic devices. In TASE, III–V materials can be grown within templates, which allows for versatility...
A laterally diffused metal oxide semiconductor (LDMOS) has been fabricated on a 12.2 μm buried oxide (BOX) silicon-on-insulator (SOI) substrate, successfully achieving a breakdown voltage of over 2000 V. This paper describes the proposed drift structure for SOI LDMOS. The proposed LDMOS drift structure adopts SOI reduced surface electric field (SOI RESURF) technology, which uses the BOX layer to establish...
In this paper, a new 1200 V-class ultra-narrow-mesas fin p-body IGBT (U-Fin-P IGBT) is proposed. Different from the previously demonstrated fin p-body IGBT, a much narrower fin (mesa) width (∼ 0.5 μm) is adopted in the U-Fin-P IGBT to further reduce the conduction loss; whereas the difficulty of doing emitter contact lithography on top of the ultranarrow mesa regions is resolved by using a self-aligned...
InAs nanowire growth is carried out on a thin grainy layer of SiOx on Si (111), utilizing the openings of pinholes in the SiOx layer by isotropic wet etching. SiOx layers with different initial thicknesses were deposited and etched down to different thicknesses, to investigate the influence of the initial layer roughness and the etching depth on the formation of pinholes and thereafter the nanowire...
We present a fabrication method for a photonic crystal membrane consisting of Er2O3/Si, and investigate the induced photonic band-gap effect. We obtain a fine photonic crystal structure by selective area growth of Er2O3 on a pre-patterned Si(111) membrane by the molecular beam epitaxy method, and the fabricated Er2O3/Si photonic crystals show the suppression of the radiative transition as a result...
The performance of a novel diode with characteristic trench shape is predicted by TCAD simulation. A novel 600 V vertical PiN diode with hole pockets by the Bosch deep trench process is proposed for a better trade-off curve between reverse recovery loss and forward voltage. The reverse recovery loss is reduced to a half. In addition, the active chip size of the novel diode is reduced to two-thirds...
The doping of n-type silicon solar cells was investigated using two ion implantation techniques: beam line and plasma immersion. Initially, we evaluated the benefits of beamline ion implantation in replacement of diffusion anneal doping process. Two different annealing routines were studied. The first one using a single annealing to activate both B implanted emitter and P implanted BSF, while the...
We propose a silicon dual-ring modulator that enables low-chirp modulation for long-haul transmission. The proposed structure is robust against fabrication uncertainty and provides chirp tailoring for specific application.
Inductor is a key passive component in radio-frequency integrated circuits (RFICs). Compared with other components in the circuit, inductor has a bigger size, hence its miniaturization is critical for integrated circuit system. Most of conventional on-chip inductors fabricated on silicon substrates are planar structures, and have low quality factor (Q) due to the substrate loss of low-resistivity...
This paper presents the design and demonstration of redistribution layers directly on the surface of glass for high-speed 28 Gbps signaling applications. An unprecedented demand for bandwidth to support cloud and edge computing driven by online services is expected with the continued proliferation of connected devices including smartphones, Internet of Things, and autonomous electric vehicles. High...
Three-dimensional integration with throughsilicon vias is becoming essential for the future of the microand nano-electronics industry. The ability to incorporate multiple wafers and systems in a single design is revolutionizing device packaging. However, the complexity in the fabrication of through-silicon via structures and the reliability concerns must be addressed. In this work the effects of the...
Driven by the need of reduced energy consumption in devices, 3D integration technology by through silicon via (TSV) attracts increasing interests. However, high thermal stress is induced by the large mismatch of the coefficient of thermal expansion (CTE) among the different materials in TSV. The thermal stress is a serious reliability concern for TSV in 3D integration system. In order to solve the...
Analyzing the concentration of acetone in human breath constitutes a promising non-invasive means to diagnose the onset of diabetes, with acetone levels of at least 1.8ppm typically associated to individuals suffering from diabetes. In this paper, we report the performance of a hierarchical ZnO nanostructure gas sensor for acetone detection. The fabricated gas sensor can detect concentrations as low...
High reflection losses and low photon absorption combined with high velocity large area surface recombination are the main obstacles for boosting the efficiency of solar cell. We report a simple large-scale one step catalytic room temperature fabrication approach of black silicon (B-Si) in an aqueous solution of HF and AgNO3. B-Si based on porous and nonporous Silicon nanowires (SiNWs) shows a superior...
We report the first observation of mode splitting in a standalone microelectromechanical resonator resulting from the coupling from a mechanical mode to intrinsic localized modes. The demonstration of this coupling mechanism in a microstructure finds its relevance in both fundamental studies including explorations of phonodynamics and applications exploiting energy localization or delocalization by...
Here we present the fabrication process for silicon-in-glass electrodes as capacitive transducers. The embedded electrodes are formed by utilizing a glass reflow process. DRIE process easily defines the number and shape of these embedded silicon electrodes. Eight, sixteen, twenty-four electrodes are obtained through this process. These silicon-in-glass electrodes are anticipated to be operated to...
In this paper, a novel Si interposer for hermetical MEMS oriented System-in-Package application is presented and it is a low stress, scalable platform with a stress releasing function. It's composed of Si posts which are Air-gapped from Si interposer substituting traditional Copper TSVs to function as electrical interconnection paths, re-distribution layer (RDL) and landing pads for chip stacking...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.