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Impact ionization [1,2], or electron-hole pair creation by charged particles, has been one of the central issues of semiconductor physics and devices. However, due to its complexity of the process, most experimental studies and their analyses have been macroscopic and phenomenological. This situation prevents us from exploring the fundamental physics of impact ionization and of high-energy charged...
We have successfully exploited multi-dimensional spaces of concentrations of the interstitial species, Si and Ge, geometries and compositions of the starting SiGe nano-pillar, and sources of Si interstitials (the Si3N4 and Si encapsulation layers) to create new classes of exciting optical and electronic devices such as single-electron tunneling devices, wavelength-tunable photodetectors, and MOSFETs.
In this paper, a three-dimensional (3-D) positioning system using fingerprinting and K-Nearest neighbor is proposed. The implementation of the proposed positioning system based on visible light communication (VLC) is discussed. On-off keying (OOK) modulation, Manchester coding and time division multiplexing (TDM) are utilized to obtain both lossless data and accurate received signal strength indications...
We report the first demonstration of real-time monitoring of a single spin in a Quantum Dot (QD) using foundry-compatible Si MOS technology and a Split-Gate design with built-in charge detector. Since single-shot readout is an indispensable step in the pursuit of Si-based fault-tolerant quantum computing, this work contributes to asserting the fabrication of Si spin qubits in a MOS technology platform...
InxGa1−xAs MOSFETs with superior carrier transport properties promise to deliver high current at reduced supply voltages [1-2]. Strained III-V quantum well FinFETs (QW-FF) have been investigated [3-4] as feasible pathways to low power logic. For sub-7 nm nodes, challenges in maintaining electrostatic integrity in FFs has led to the proposal of faceting the FF channel (corrugated channel) to produce...
We report, for the first time, a gate last process, used to fabricate Negative Capacitance field effect transistors (NCFETs) with Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration. Long channel NCFET's with HZO thickness down to 5 nm exhibit consistent switching behavior with switching slope (SSrev) below kT/q over four decades...
The unprecedented technological success of the electronics industry over the last five decades have been driven by Silicon (Si) technology at the center of which resides the metal oxide semiconductor field effect transistor (MOSFET). Relentless scaling of MOSFET dimensions ensured faster and cheaper computing since more and more transistor could be packed into the same chip area.1 At the same time...
Germanium is a promising material for future VLSI devices, due to its high hole mobility. However, due to the low bandgap of 0.66 eV Ge based devices typically suffer from high reverse junction leakage und therefore high static power dissipation. In this paper, we apply a nanowire structure with multiple independent gates to suppress the leakage in off-direction to achieve off-current levels below...
In this paper, we demonstrate for the first time an implant free In0.53Ga0.47As n-MOSFET that meets the reliability target for advanced technology nodes with a max operating Vov of 0.6 V. In addition, an excellent electron mobility (μeff, peak=3531 cm2/V-s), low SSlin=71 mV/dec and an EOT of 1.15 nm were obtained. We also report the scaling potential of this stack to 1nm EOT without loss of performance,...
We present vertical InAs nanowire MOSFETs on Si with an In0.7Ga0.3As drain. The devices show Ion and gm/SS record performance for vertical MOSFETs and Ioff below 1 nA/μm at Vd 0.5 V. We show a device with gm=1.4 mS/μm and SS=85 mV/dec, therefore having Q-value (gm/SS) of 16. The device has Ion=330 μA/μm and 46 μA/μm at Ioff 100 nA/μm and 1 nA/μm, respectively. Furthermore, we show a device with SS=68...
Metal-oxide-nitride-oxide-silicon (MONOS) type memory is a promising candidate to replace the conventional floating-gate (FG) type non-volatile memory [1]. Even for MONOS memory with high-k gate stacks, such as the in-situ formation of Hf-based MONOS structure, the scaling is necessary to reduce the operating voltage [2]. However, as the gate stacks scaling, the interface roughness at the gate insulator/Si...
We demonstrate scaled high-Ge-content (HGC) strained SiGe pMOS FinFETs with very high short channel (SC) performance using a Replacement High-K/Metal Gate (RMG) flow, for the first time. A novel RMG gate stack process was introduced to create Ge-free interface-layer (IL) with excellent reliability and sub-threshold swing (SS) as low as 62mV/dec, the best reported to date for Si-cap-free SiGe FinFETs...
The HES-SO Valais has installed a PV-generator, where each PV-module is individually linked to the 700V DC-bus power line via an individual DC/DC voltage converter with integrated maximum power point tracker. A battery storage system is connected to the DC-bus for local energy storage. The polar +/−350 V DC bus voltage is controlled by an AC/DC converter interfacing the system to the low voltage AC...
Field-effect transistors (FETs) are commonly used as affinity-based electrical transducers, known as bioFETs. These sensors are, however, unable to directly detect uncharged molecules such as glucose, necessitating the use of ligand molecules. Further, the change of the electrical signal resulting from the biochemical reactions is often small. In the past decade, significant research was done to enhance...
An input/output characteristics of the inverter composed of the DNA/Si-MOSFET and the parasitic capacity was studied. The DNA was bridged between the Si electrodes those serve as the source and drain with the 120nm-gap-length. At VDD=0V and VDD=3V, the output characteristic was almost the same. The reason of this phenomenon is that the space charge layer of the DNA/Si-MOSFET changes due to the charge...
We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly...
In this paper, we present a new local layout effect in 14nm FinFET due to different CT layout designs (CT extension, CT spacing, and PC past RX distance). Based on 14nm FinFET experimental data, the CT LLE effect induces up to 50mV Vtsat shift, and ∼20% current change. NFET performance is enhanced by ∼7%, while the PFET performance shows slight degradation. Based on TCAD simulation, the CT LLE is...
The world's first GeSn p-FinFETs formed on a novel GeSn-on-insulator (GeSnOI) substrate is reported, with channel lengths Lch down to 50 nm and fin width WFin down to 20 nm. In comparison with other reported GeSn p-FETs, record low S of 79 mV/decade, record high Gm, int, of 807 μS/um (VDs of −0.5 V), and the highest Gm, int/Ssat, were achieved. The highest high-field hole mobility of 208 cm2/Vs (at...
Recent embedded ReRAM has a small resistance-ratio (R-ratio), which results in a small read sensing margin (ISM). A larger BL current (IBL) increases the input offset (IOS) of current-mode sense amplifiers (CSA), resulting in low-yield read operations and long read access times (TCD). This work proposes an IBL-aware small-IOS CSA, using a dynamic trip-point-mismatch sampling (DTPMS) scheme to increase...
Intelligent connected sensor and actuator endpoint nodes enable the Internet-of-Things (IoT). A brief overview of endpoint node functional blocks and requirements for low-power consumption are discussed. VLSI technology enablers for IoT include Ultra low Power (ULP) and Ultra Low Leakage (ULL) semiconductor process platform extensions. ULP and ULL implementations for bulk silicon technologies are...
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