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We propose to integrate silicon nitride on silicon-on-insulator platform for devices which require low insertion loss and high power handling capability. Preliminary results including silicon nitride growth, high-Q resonator fabrication, and vertical integration are presented.
We report on the design, fabrication and characterisation of submicron silicon-on-insulator strip waveguides at a 3.74 µm wavelength. Experimental results for 1×2 multi-mode interference splitters are also given.
The combination of CMOS compatible Silicon-On-Insulator (SOI) fabrication technology with organic cover materials constitutes the Silicon-Organic Hybrid (SOH) fabrication platform, which shows innovative functionality for the making of integrated optical circuits. We report on experimental demonstrations of essential building blocks for transceivers, while relying only on well-known SOI processing...
Due to their out-standing performance (huge bandwidth and high signal quality), optical communications have become the standardized technologies suited for long reach and high bit-rate communication systems. Nevertheless, the traditional incompatibility of CMOS with the optical technology, and the difficulty for all-optical implementation of some key functions such as buffering and header processing,...
Two-step reactive ion etching process has been optimized to demonstrate small cross-section single-mode silicon waveguides. This technique has helped to reduce the insertion loss of compact integrated photonic devices in SOI platform up to 3 dB.
A dual mode device has been realized with FDSOI MOSFET technology implementing both a single electron transistor (SET) and a field effect transistor (FET). The silicon substrate is used as a back gate to choose between these two functionalities. We show in this paper that the behavior of the device is determined by the position of the electron gas in the silicon mesa: the device is a SET if the electron...
In this paper appropriate alloys of germanium (Ge) and silicon (Si) have been investigated and applied in silicon-on-insulator (SOI) technology for homogeneous optical sensing at 2.883 μm. Novel vertical slot waveguides have been analyzed, in particular their optimization in order to achieve ultra-high sensitivity as well as relaxed fabrication tolerances. These features have been compared with well-known...
In this paper we report propagation and bend loss measurements for silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) waveguides at 3.39 µm wavelength. Preliminary experimental results for SOI rib waveguides at around 3.8 µm are also given.
We report a 40 Gb/s optical modulation with similar performance for TE and TM polarisation using a depletion diode inserted in both arms of a Mach Zhender interometer.
In MEMS industry, silicon-on-insulator (SOI) wafers are gaining ground from blank silicon wafers as the main starting substrate. Tailored SOI wafers available in the market contain for example buried cavities or a buried gettering layer. Adding another layer in addition to the thermal SiO2 insulator, or replacing it with another material altogether, could be a way to tailor the properties of SOI wafers...
We demonstrate here the fabrication of integrated tracking (horizontal) and focusing (vertical) micro lens actuators which are implemented on silicon-on-insulator (SOI) wafer using silicon bulk micromachining. The micro actuators that consist of flexures, a lens holder and comb structures with electrodes can realize two-dimensional movements of one objective lens for optical storage applications....
Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCut™ technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 Å on preproduction volume. Total thickness variation of ± 5 Å is targeted.
The effects of ultrathin EOT on the carrier mobility in bulk-Si, UTBOX-FDSOI and SiGe-QW pFET devices were compared. The mobility is found to decrease dramatically with the EOT (Tinv) as a result of stronger charge and surface roughness scattering at thinner SiOx interface layers irrespective of the device technology. UTBOX-FDSOI and bulk-Si nFETs have identical mobility values (190 cm2/Vs) at Tinv...
A novel design of switched-line RF-MEMS (radio frequency micro electro mechanical systems) phase shifter for the X-Ku band (8 ~ 18 GHz) has been successfully developed by monolithically integrating electrostatic micro actuation mechanism of MEMS with a movable coplanar waveguide made of single crystalline silicon. MEMS and RF designs have been performed with minimum geometrical conflicts thanks to...
There is consensus in the IC industry that fully depleted devices will be the solution to the increasing challenges of device scaling towards nodes 20nm and 15nm. Fully depleted (FD) devices with undoped channels eliminate the threshold voltage VT variability due to random dopant fluctuation (RDF) reducing the overall VT variability by over 60%. For a given power supply FD devices have superior short...
We describe the fabrication of radiation dosimeters utilizing fully-depleted silicon-on insulator (FDSOI) substrates, and further demonstrate the detection of various ionizing radiation types including protons, a-particles, and X-rays by the threshold voltage (Vth) changes caused by the radiation-induced charge trapped in the buried oxide. Our FDSOI dosimeter exhibits a sensitivity of ~3 mV/krad(SiO...
The silicon MOS transistors for VLSI have been scaled down for more than forty years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length is now less than 30 nm. The silicon devices are certainly in the nanometer regime. Fig. 1 shows technology nodes and gate length according to ITRS [1]. It is predicted in the 2009 version of ITRS that the gate length...
The chemical reactions at the higher-k LaLuO3/Ti1NX/poly-Si gate stack interfaces are studied after high temperature treatment. A Ti-rich TiN metal layer degrades the gate stack performance after high temperature annealing. The gate stack containing TiN/LaLuO3 with a near stoichiometric TiN layer is stable during 1000 °C, 5s anneals. Both electrical and structural characterization methods are employed...
In this paper, a new surface potential based compact model for long channel fully depleted SOI MOSFET with lightly doped ultra-thin body is presented. The 1-D Poisson equation is solved using the appropriate boundary conditions, and a closed-form surface potential solution is proposed for the front and back surface potentials. Finally the model was compared to numerical simulations and a good agreement...
In this work a non-local band-to-band tunnelling model has been implemented into a full-band Monte Carlo simulator. Two different approaches for the choice of the tunnelling path have been implemented and their impact on the transfer characteristics of different Tunnel FET structures is investigated. In both the SOI and the DG TFET architectures we have simulated, up to 1 order of magnitude of underestimation...
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