The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Paper analyzes substantial Coss behavior differences of FETs using super-junction Si, SiC and GaN technologies versus traditional Si process and suggests new practical models for power losses optimization. These models applied to derive normalized ZVS conditions and boundaries for popular PWM ZVS topologies allowing efficiency optimization at wide operating conditions.
In this work, we have shown that plasma-wave transistor (PWT) operates as a terahertz (THz) emitter below maximum gate length (Lmax). Because the channel mobility (μ) of strained silicon (sSi) is higher than silicon (Si), we investigate how emission frequency range and Lmax of sSi PWT THz emitter are improved compared to Si PWT THz emitter by analyzing the effect of momentum relaxation time (τp) and...
For more than four decades, Complementary Metal-Oxide-Semiconductor (CMOS) Field Effect Transistors (FETs) have been the baseline technology for implementing digital computation systems. CMOS transistors natively implement Not-AND (NAND)- and Not-OR (NOR)-based logic operators. Nowadays, we observe a trend towards devices with an increased set of logic capabilities, i.e., with the ability to realize...
True Single-Phase Clock (TSPC) Flip-Flops, based on dynamic logic implementation, are area-saving and high-speed compared to standard static flip-flops. Furthermore, logic gates can be embedded into TSPC flip-flops which significantly improves performance. As a promising approach to keep the pace of Moore's Law, functionality-enhanced devices with multiple independent gates have drown many recent...
A flip-flop achieving high-speed backup utilizing a Si transistor and long-term retention with zero standby power by means of a transistor of c-axis aligned crystalline (CAAC) In-Ga-Zn oxide, a kind of CAAC oxide semiconductor, featuring extremely low off-state current is proposed. Using the flip-flop, a 32-bit processor has been fabricated with 350-nm Si/180-nm CAAC oxide semiconductor technology,...
A double-pulse technique for the I/V characterization of GaN-based transistors is adopted for the nonlinear modeling of a 0.25 µm AlGaN/GaN on SiC FET. Experimental validation is provided by means of large-signal PA performance prediction both at low-frequency, in order to outline the role played by the resistive drain current source, and at microwaves. Improved prediction accuracy is demonstrated...
We report novel FETs with a structure in which not only the top surface but also the side surfaces of island-shaped c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) serving as a channel are surrounded by a gate electrode, that is, surrounded channel CAAC-IGZO FETs. The FETs maintained their favorable subthreshold characteristics even if the channel length was scaled down to approximately...
The carrier behavior in DNA was examined using the DNA channel/SiO2/Si gate structure. The source/drain electrodes with a gap of 120 nm etching a SOI film was prepared and DNA was fixed between the electrodes. The dID/dVD shows the maximum value at the drain voltage of 0.3 V. This phenomenon relates to the trapped and detrapped electrons in DNA. The electrons were trapped by guanine-base, and they...
Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presnts “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology...
Point of load (POL) converters are required smaller size and high efficiency performance in IT industrial applications, etc. Interleaved technique, magnetic integration techniques and application of GaNFETs are well known as good approaches to satisfy these demands. Although coupled inductors for POL converters have been proposed in several studies, a coupled multilayer chip inductor has not examined...
Compared with Si MOSFET, the GaN FET devices have advantages in the electrical characteristics, thermal properties and mechanical properties. This paper compares electrical properties of the GaN FET and Si MOSFET. Evaluation of the GaN FET based on flyback-forward high gain DC/DC converter at soft-switching condition are presented in detail. In addition, the power loss analysis of GaN FET based flyback-forward...
In this paper, we propose and demonstrate by simulation an electrostatically doped and therefore voltage-programmable planar field-effect-transistor (FET) structure which is based on our results of already published Si-nanowire (SiNW) devices. The key technology for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator (SOI) platform. The desired transistor type,...
In this paper, a novel double gate tunnel field effect transistor (DGTFET) configuration with p+-layer in the channel is proposed and investigated. The proposed structure is a Si-channel DGTFET, which has a p+-layer in the channel connected to the P+ source region in order to achieve improved switching and higher ON-current when compared to a conventional TFET. The simulation results of DGTFET with...
A Dual-gate graphene field effect transistor was fabricated with HfO2 and SiO2 as the back and top dielectric layers on silicon substrate, respectively. The CVD grown graphene was transferred a process by spin-coating a PMMA layer. The electrical properties of the graphene transistors were investigated. Ambipolar behavior of field effect transistor is demonstrated with the carrier mobility of the...
The aim of this work is to analyze the electric field and electric potential distributions in undoped silicon nanowire Schottky barrier field-effect transistors (SB-FETs) with a backgate configuration covered by chemical compound for sensor application. In this work we model porphyrin-coated silicon nanowire FETs (SiNW-FETs) and examine how the porphyrin covering the surface of the SiNW-FETs influences...
Rapid advancement of gallium nitride (GaN) based device technologies enables the possibility to design inverters that have superior performance capabilities compared to Si-based inverters. It is prevalently acknowledged that GaN-based switching devices outperform the Si-based counterparts in many aspects such as lower power consumption, and faster switching frequencies. GaN devices will benefit many...
LLC Resonant converters have been popular in recent years by providing highly-efficient, compact isolated power conversion for numerous applications. 48V to 12V and 400V to 12V step-down isolated converters are often required in server, telecom and automotive applications. While the switching losses in LLC converters are eliminated due to zero-voltage switching, the primary-side switch output capacitance...
Reconfigurable fine-grain electronics target an increase in the number of integrated logic functions per chip by enhancing the functionality at the device level and by implementing a compact and technologically simple hardware platform. Here we study a promising realization approach by employing reconfigurable nanowire transistors (RFETs) as the multifunctional building-blocks to be integrated therein...
The monolithic integration of III-V nanowires on silicon by direct epitaxial growth enables new possibilities for the design and fabrication of electronic as well as optoelectronic devices. We demonstrate a new growth technique to directly integrate III-V semiconducting nanowires on silicon using selective area epitaxy within a nanotube template. Thus we achieve small diameter nanowires, controlled...
For devices beyond the 14nm node, it is important to investigate performance boosters such as high mobility channels. Although pure Ge offers a higher hole mobility than Si, conventional problems like surface passivation and its integration with Si makes SiGe alloy with low Ge mole fraction a viable option. The significance of alloy scattering, however, has been widely debated [1–3], so the accurate...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.