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Thin film deposition process invariably introduces compressive or tensile stress in the films. The stress in a film causes the wafer to warp whose curvature is estimated in a wafer fab using optical reflectance technique. Alternatively, the wafer curvature can also be measured using the high resolution XRD (HRXRD) Si(004) rocking curves. In this paper, the HRXRD technique was employed to evaluate...
This is a case study of an early failure analysis on a chip fabricated on the 40nm technology node. A large leakage current was observed in the high voltage (HV) supply after the chip was stressed as a part of an early failure rate (EFR) test. Electrical failure analysis (EFA) using Backside Emission spectroscopy [1] and Optical Beam Induced Resistance Change (OBIRcH) [2] showed the existence of hotspots,...
We report on a 32-MHz quartz TCXO fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ± 0.2 ppm over temperature using on-chip third-order...
Ultra-thin wafer (thickness <100 µm) gripper is a challenging component to design since the wafer is one of the thinnest and fragile materials. In this paper, a soft acting non-contact gripper based on the distributed Bernoulli principle for ultra-thin wafer is developed and evaluated. The theoretical analysis and experimental studies of the designed gripper are carried out. The effects of the...
An internal paralleled active neutral point clamped converter (IP-ANPC) is presented in this paper. Advantages of the IP-ANPC converter include modularity, reliability and efficiency improvement, capability of interleaving, and better utilization of wide band-gap (WBG) devices. To simplify the operation of the IP-ANPC converter and provide an easy interleaving solution, a logic-based flying capacitor...
The area of flexible electronics is rapidly expanding and evolving. With applications requiring high speed and performance, ultra-thin silicon-based electronics has shown its prominence. However, the change in device response upon bending is a major concern. In absence of suitable analytical and design tool friendly model, the behavior under bent condition is hard to predict. This poses challenges...
The unprecedented technological success of the electronics industry over the last five decades have been driven by Silicon (Si) technology at the center of which resides the metal oxide semiconductor field effect transistor (MOSFET). Relentless scaling of MOSFET dimensions ensured faster and cheaper computing since more and more transistor could be packed into the same chip area.1 At the same time...
Three-dimensional (3D) ICs using TSVs are the most promising candidate for high performance and low power computing since they have lots of advantages such as short wiring length, small chip size, and small pin capacitances, as shown in Fig. 1 [1]. Until now, several kinds of 3D-ICs including image sensor chip, shared memory, and retinal prosthesis chip have been fabricated successfully.
Thermo-mechanical stress accumulation in the power electronic integrated circuit (PIC) devices influences their lifetime and reliability. In order to determine both the temperature and the stress accumulation, numerical simulation is a very important tool in the design of PIC devices for quantifying and enhancing their lifetime and reliability. An open source solution integrated in Salome-Meca and...
State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS®) has been applied for the first time in fabricating high performance wafer level system-in-package (WLSiP) containing the 2nd-generation high bandwidth memory (HBM2). An ultra-large Si interposer up to 1200 mm2 made by a two-mask stitching process is used to form the basis of the 2nd-generation CoWoS® (CoWoS®-2) to...
Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active...
In this work, a system assembly technology will be presented that allows an effective mechanical decoupling of the MEMS element from the environment while maintaining minimal package footprint and cost. It utilizes a Si interposer with planar spring structures for an independent suspension of all interconnects to the MEMS element. The design of the planar springs was optimized for maximum stability...
We have developed a novel fan-out wafer level packaging (FOWLP) technology for high-performance and scalable flexible and biocompatible substrates that we call FlexTrate (TM). We demonstrate the technology with the assembly of 1-mm-sqaure 625 (25 by 25) Si dielets on a biocompatible Polydimethylsiloxane (PDMS). By using the new FOWLP technology, die-die interconnects with a pitch of 10 mm or less...
In this paper, the pumping behaviors of copper filler from TSV were systematically investigated. First, in-situ observation of copper pumping from TSV was conducted in scanning electronic microscope (SEM), the pumping height of copper filler and its evolution with time and temperature was recorded, it is found that the pumping rate increase with temperature and the maximum pumping height reached 12...
X-Ray Diffraction (XRD) is a very efficient experimental tool for strain/stress analysis at different scales, which makes possible to carry out some mappings in complex 3D flip chip assemblies. First, with single crystal method, both the chip and the substrate have been analyzed at the same positions, considering a 1mm2 step, in order to quantify the level of stress inside. Then Kossel microdiffraction...
Fan-out wafer level packaging (FOWLP) not only provides simplified supply chain management and lower cost structure, but also enables thinner profile and heterogeneous system integration. FOWLP is becoming increasingly significant and is projected to drive growth in advanced packaging for the foreseeable future. There are many different processing technologies for fabricating FOWLP. One common key...
High thermo-mechanical stresses are usually induced in through silicon via (TSV) structures due to the mismatch of coefficients of thermal expansion (CTE) between copper and silicon in Cu filled TSVs, which has brought an increasing concern for the reliability problems during fabrication process and operation of electronic devices. The size, shape and orientation of Cu grains in TSVs and their effects...
Emerging fan-out packages require advances in mold compounds, polymer interfaces to metals and silicon, and innovative processing to reach the required high reliability. In this paper, we discuss the fracture energy for mold compound interface to copper and silicon, and use that information for studying interfacial delamination propagation of mold compound. We have examined mold compound delamination...
In this paper, finite element method (FEM) simulations are carried out with pillar-concave structure using silicon substrate, silicon substrate with polyimide (PI) and with polybenzoxazole (PBO) for realization of Cu-Cu bonding at low temperature. Parameters of bonding temperature, pillar diameter, concave sidewall angle, and multilayer of concave structure are all considered in simulation. In addition,...
Reliability analysis is performed for various redistribution layer (RDL) interconnect patterns. Five different RDL patterns are designed to examine die pitch, line length, line width, dummy block, and die edge/corner effects on RDL reliability. Temperature dependent material properties, grain growth induced stress, thermal mismatch stress, and plastic deformation evolution are taken into consideration...
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