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In this paper the effect of low k dielectrics on Quality factor is studied using multi level interconnect technology. With low-K dielectric we achieved improvement in the Quality factor of spiral inductor at higher frequency. From the simulation results the proposed inductor using low k dielectric achieved high Q with 100% improvement when compared with basic CMOS process on chip inductor. The percentage...
This paper presents the concept of a new field effect transistor (FET) based on ferroelectric insulator. The proposed design is a Partially Depleted Silicon-on-Ferroelectric Insulator Field Effect Transistor (PD-SOFFET). The design combines the concepts of negative capacitance in ferroelectric material with the design of a partially depleted silicon-on-insulator (PDSOI) device. In this structure we...
A piezoelectric MEMS with wake up function, Power down interrupt generator (PDIG), for inertial sensor systems is reported. The aluminum nitride based MEMS generates electric signals intrinsically in result of an inertial accelerations. The PDIG is optimized for maximum charge and voltage sensitivity. The charge sensitivity for a single electrode designed PDIG is measured with 40.1 pC/g and the maximum...
In this paper, the package solutions for die-to-die interconnection including fine-line substrate and ASE advance wafer level package (aWLP) have been purposed. The fin-line substrate has 3um trace width and 3um trace space on top layer with copper interconnection. For aWLP, the trace width and space of interconnection on redistribution layer (RDL) is the same with fine-line substrate. The different...
Recent communication for cloud computing strongly requires an order of magnitude wider bandwidth than current one, such as over 28Gbps in SerDes and Interiaken protocols. So the IO transmitter and receiver becomes to one of key issues. In generally, those high bandwidth IO systems consume relative high power due to relate with fCJ⁁2 by CMOS transistor and parasitic capacitances. Additional problem...
It is very much important to design an efficient and reliable power conditioner with detailed study on measurement of AC parameter of solar cell (especially the cell capacitance). In this paper, we measured the capacitance of GaAs/Ge and Silicon (BSFR) solar cells under dark condition over a wide range of bias voltages using low level sine wave signal of desired amplitude. The approach of sinusoidal...
This paper reports an up to 95.9% angle detection accuracy enhancement for capacitive tactile sensors, which entails asymmetric and intentionally shifted electrodes. The rotational shift between two electrodes of a capacitor that greatly contributed to angle detection errors was theoretically analyzed and examined by experiments with simulations. The asymmetric electrodes containing one fan- and one...
This paper presents fabrication and characterization of Tobacco mosaic virus (TMV)-templated hierarchical nickel oxide (NiO) supercapacitor electrodes. The hierarchical NiO electrode was created by integrating silicon (Si) micropillars with thermally oxidized nickel (Ni)-coated TMVs. SEM images taken after the high temperature oxidation process verified the robustness of the bio-nanotemplates, while...
SiC MOSFET can switch five to ten times faster compared to state of the art Si IGBT. Due to that SiC MOSFET based power converter can be lighter in weight, highly efficient, compact in size compared to Si IGBT based power converters. But the parasitic inductance in the power circuit will not allow SiC MOSFET to switch to its full potential due to very high device voltage overshoot, sustained oscillation...
This paper presents the Modeling of Silicon capacitive pressure sensor for biomédical applications. Using the Micro Electro Mechanical Systems (MEMS) technology, MEMS sensors are widely used in biomédical applications due to its advantages of miniaturization, low power consumption, easy to measurement and telemetry. This work demonstrates the design of MEMS based capacitive pressure sensor using finite...
Micro interdigitated electrodes (IDE's) have successfully been fabricated and characterized amperometrically for the electrochemical detection of the pH concentration and bio-molecules. In the present work, aluminium (Al) is used act as the metal contact (electrodes) deposited on the silicon substrate using a thermal evaporator (PVD) vacuum coater. The simple conventional photolithography was applied...
Inspired from Through Silicon Vias (TSVs), Through Silicon Capacitors (TSCs) are newly developed capacitors integrated throughout the silicon interposer. This paper deals with a demonstrator which investigates the first process steps of TSCs. A predictive modeling method of the impedance of large matrices of such components is proposed. The modeling method makes use of 2D/3D parasitic extraction software...
In this paper, we report the potential of the doping-less (DL) double gate field effect transistor (DL-DGFET), for ultra low power (ULP) subthreshold logic applications. We demonstrated that the proposed DL-DGFET do not require any doping from source to drain region and it can perform significantly better than highly doped junctionless (JL) and abrupt S/D inversion-mode (IM) DGFETs. The DL-DGFET achieves...
This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically...
In this paper, investigation of Parylene-HT for using as insulation/liner in through-silicon-via (TSV) is presented. Bottom-up copper filled TSVs with 1 µm Parylene-HT insulator with aspect ratios (ARs) up to 10, are demonstrated on a 100 µm-thick Si wafer through via etching, parylene vapor deposition, and copper electroplating processes. Cross sectional inspections on the fabricated TSVs confirm...
In this paper, we propose and investigate a novel device structure for silicon-on-ferroelectric Tunnel FET (SOFTFET) based on the negative capacitance effect of the ferroelectric layer. The conduction mechanism of proposed device is based on the combined effect of two mechanisms namely, tunnelling and negative capacitance effect. Thus, it achieves a steep subthreshold slope (SS) of 13.9 mV/dec at...
This paper introduces a novel concept of threshold voltage variation analysis using stacked-FET Power amplifier (PA). In this work, a conventional adaptive biasing circuit is merged with two stacked FET which controls and minimizes the fluctuations of the threshold voltage variation for class AB PA. Analytical equations are derived to achieve much less variation of threshold voltage shift. Comparisons...
Lumped analytical electrical models for partially cracked and void hole defected TSVs are proposed in this paper. Accurately modeling defects may enhance the test methodology and could be vital to improve the quality of TSV-based 3D-ICs. These models were verified by simulations using a commercial 3D resistance, capacitance and inductance extraction tool. The presented simulation results are in close...
In this study, Parylene-HT, the newest commercially available parylene with the lowest dielectric constant and highest temperature tolerance within all the series, was investigated as insulation/liner in the application of through-silicon-via (TSV). Bottom-up copper filled TSV with 1 µm Parylene-HT insulator was realized on a 100 µm-thick Si wafer through via etching, parylene vapor deposition, and...
To improve immunity against process gradients, common centroid constraint, in which every pair of elements should be placed symmetrically with respect to a common center point, is widely used. Several methods to obtain a good placement satisfying the constraint by using sequence-pair and Simulated Annealing were proposed. However, cells in a common centroid group should be placed close to the common...
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