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An equivalent circuit model of through silicon via considering the eddy current flow inside the silicon is proposed to predict the electrical performance up to 100GHz. The parasitic elements of the proposed circuit model are derived by the structural dimensions and material properties of the TSV, and its electrical performance of the proposed equivalent circuit model is analyzed with structure size...
This paper discusses the concept of the inversion coefficient IC as an essential design parameter that spans the entire range of operating points, from weak, via moderate, to strong inversion. Several figures-of-merit (FoMs) including the Gm/ID, the Ft and their product Gm/ID · Ft are presented and modelled in terms of IC, including the effect of velocity saturation. These FoMs incorporate the various...
This paper presents a methodology to characterize the electrical behaviors of mixed conventional and coaxial through silicon vias (TSVs) network in three-dimensional (3-D) integrated circuits. An equivalent circuit model is established to predict the insertion loss and crosstalk level of the mixed TSV network. By the proposed model, the shielding effectiveness of the outer conductor in coaxial TSV...
Increasingly stringent requirements for higher power density and efficiency have driven development for lower on-resistance (Ron) and gate charge (Qg) power transistors. Gallium Nitride (GaN) and Silicon Carbide (SiC) are good contenders for replacing conventional Si power transistors. This work attempts to develop a driver IC to fulfil specific needs of Gallium Nitride Gate Injection Transistor (GIT),...
Modeling of parasitic semiconductor device capacitances has always been a difficult task due to their nonlinearities. In this paper, we present a novel charge based model which provides simplification and ease of the modeling process. Further-more, convergence errors are reduced and the simulation speed is enhanced by up to a factor of two compared to state of the art models. This is especially important...
Verilog-A based unified compact model of silicon vertical nanowire FET is developed for circuit simulation, which includes: short channel, velocity saturation, mobility degradation, quantum mechanical effects and device parasitic. We include scalable TCAD calibrated parasitic resistance and capacitance models, which also consider device asymmetry due to vertical nanowire structure. The model shows...
This paper presents a method aiming to detect different inter-turn short circuit fault severity by analyzing zero-sequence voltage for a new five-phase fault-tolerant fractional-slot concentrated winding interior permanent magnet motor (FTFSCW-IPM). To eliminate the effect of common mode voltage (CMV) in single DC power supply application, fault severity analysis is conducted based on an open-end...
Inductances of a multiple coupled circuit machine model are calculated from its magnetic equivalent circuit. The modeled considers an electric machine with semi-closed slots.
The calculation of the inductances of a multiple coupled circuit machine model based on its magnetic equivalent circuit is presented in this paper. This approach allows to take into account the winding distribution as well as core and airgap saliencies. In order to validate the proposal, induction machine inductances were calculated and compared with those obtained by the winding function approach...
A geometric approach of the well known winding-function approach for the calculation of electric machine inductances is presented in this paper. An elementary induction machine is used in order to validate the proposal.
This paper presents an averaged model for a coupled-inductor double-boost converter. Differential equations depend on the time intervals for which diodes are conducting simultaneously. Thus, expressions that permit to estimate those values as a function of the states of the circuit are also proposed. The response of the model is compared with that of the original converter via numerical simulations.
Over recent years, spin-MOSFETs (Fig.1) [1] have attracted considerable attention as a key transistor for low-standby-power integrated circuits. To realize spin MOSFETs, understanding and controlling of spin dynamics in the Si channel is indispensable. The Hanle effect of spin-polarized electrons transported in the channel of spin devices is a powerful tool for evaluating spin dynamics. Using the...
Reconfigurable Silicon nanowire Schottky Barrier transistors (RFETs) with configurability to be programmed as n/p-type polarity are promising for future integrated circuits. In this work, the tunable polarity characteristics of RFETs are investigated. TCAD simulations have been performed for RFETs-based INV, NOR, NAND logic gates and SRAM cell. 4-terminal RFETs presented show the potential of programmable...
In this paper, the terahertz (THz) detection based on Silicon MOSFET is investigated with two-dimensional (2D) ensemble Monte Carlo (MC) simulation study. The analytical model of responsivity to high frequency small signals based on the small-signal equivalent circuit of MOSFETs operating in terahertz detection mode are developed and calibrated. We explore the impacts of input excitation signals with...
The dimensional evolution of device has increased the importance of TCAD simulation and its multilateral expansion to process and design domains. Challenges for achieving virtual silicon as a holistic simulation analysis and recent progresses are discussed.
High speed and low power transmission on optical interconnections can be achieved using ring-based optical modulators. 3D-integration of the ring modulator on top of the driver chip allows compact and cheap transmitters. 4-PAM modulation is considered for the first time for a high data rate.This paper presents a 10 Gb/s ring modulator driver with high and adjustable swing. The circuit is designed...
Silicon nanowire FET (SiNWFET) with dynamic polarity control has been experimentally demonstrated and has shown large potential in circuit applications. To fully explore its circuit-level opportunities, a physics-based compact model of the polarity-controllable SiNWFET is required. Therefore, in this paper, we extend the solution for conventional SiNWFETs to polarity-controllable SiNWFETs. By solving...
Abstract- the using radionuclide sources of alpha radiation was justified to neutron irradiation simulation on silicon semiconductor devices and integrated circuits. A general approach was formulated to use these sources for dose space radiation simulation.
We present 1.55 μm hybrid III-V/Si SOA designs and experimentally determine wall-plug-efficiency (WPE) values for 2 mW and 0.1 mW input power amplification. Flared SOAs yield WPE = 12.1% for output power > 10 mW and straight SOAs achieve WPE = 7.2%.
Closed-form expressions of the parasitic insulator capacitance and the substrate capacitance for tapered through silicon vias (TSVs) are proposed. The expressions are functions of the geometric and material parameters of TSVs. They also can be applied to the cylindrical TSVs when the slope angle is zero. The two parasitic capacitances increase as the slope angle increases, which implies that the tapered...
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