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This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It uses an input transformer to reduce ground bounce effects and operates around 1 W of output power. A tuned driver stage provides impedance matching to the input signal source and proper gain to the next stage. A control stage is used for...
This paper presents a 56Gb/s 16-QAM 65nm CMOS transceiver using a W-band carrier. Two wideband IF signals are up- and downconverted simultaneously with 68GHz and 102GHz carriers. The transceiver achieves 56Gb/s data-rate with TX-to-RX EVM of −16.5dB within 0.1m distance. The transceiver consumes 260mW and 300mW from a 1V supply in TX and RX modes, respectively. This results in 10pJ/bit efficiency,...
This paper presents a CMOS cross-coupled film bulk acoustic resonator (FBAR) oscillator which was designed in class-C topology in order to improve phase noise and power consumption. The designed class-C FBAR oscillator shows lower phase noise with the same power consumption than that of a comparatively designed class-B FBAR oscillator. The efficient current generation in class-C leads to the improvement...
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational transconductance amplifier (OTA) is one of the most important components of this ADC. This paper reports a new design of low power fully differential OTA. In this design authors have used adaptive biasing technique and DC gain enhancement technique for improving design parameters as compared...
In this paper continuous time high-performance current mirrors (CMs) based on series and parallel connected unity sized CMOS transistors suitable for low power applications are presented. It is shown that the proposed implementation techniques allow an increased output resistance, from twice the output resistance of the simple current mirror (SCM) up to more than 50 times of the cascode current mirror's...
This article discussed a multilevel transistor clamped H-bridge topology for DVR application along with repetitive controller. This five level TCHB inverter topology can be used for low and medium voltage level application of DVR. The repetitive controller used in this paper for DVR application can compensate the three major voltage quality disturbances such as balanced voltage sag, voltage harmonics...
This paper reports the analyses of two techniques for phase noise reduction in the CMOS Hartley oscillator circuit topology. Namely, the two techniques, noise filter and optimum current density are investigated with the objective of exploring the potential benefits in the mm-waves frequency range. The design of the circuit topology is carried out in 28 nm bulk CMOS technology by STMicroelectronics...
With the emergence of energy-starved systems like wireless sensor nodes, it becomes much more of a necessity for important blocks in such systems like the voltage reference (VR) to work at an ultra-low power consumption. Furthermore, the varying requirements of the functional blocks of a wireless sensor node (WSN) entail varying VR requirements, therefore flexibility in the design of VRs is required...
This paper presents a new LNA architecture comprise current reuse topology. The design is carried out in BSNIM3 180 nm CMOS technology. The proposed LNA consumes less power of 12.49 mW as compared to other existing architectures, while providing better gain (16.78 dB) and low NF i.e. less than 5 dB over the frequency range of 3 to 10 GHz. The design offers power gain (S21) of 7.5 dB and input return...
In this paper, a simple filter topology that can be used to implement first-order MOS-only allpass filter is proposed. The proposed MOS-only allpass filter offers inherently very accurate magnitude and phase characteristics at very high frequencies. However, MOS-only active filter suffers from an inherent low frequency limitation. In order to address this issue, the modification technique allowing...
This article presents a new class of hybrid converters named Switched-Linear (SL) Converters that can operate as a DC-DC, DC-AC or AC-DC converter. The idea is originated from conventional linear power amplifier integrated with a switched power converter. The linear power unit/cell is a power amplifier, which is fed by two tracking power supplies to boost the efficiency of the linear unit without...
This paper deals with a proposal of a carrier redistribution PWM and its comparison with a phase disposition PWM (PDPWM) and carrier redistribution PWM for a multilevel converter dedicated to high power medium voltage electric drives. The converter topology is based on a cascaded connection of two-level inverters, the so called dual inverter. The well known phase disposition PWM for multilevel converters...
The paper introduces a novel boost topology exhibiting comparable efficiency but lower semiconductor voltage stresses compared to the classical boost converter. Operation of the converter in continuous conduction mode (CCM) is similar to that of the classical hard-switched PWM converter, except for the fact that a resonant interval is introduced in the first topological state. After all design equations...
This paper presents a resistorless bandgap reference with minimized quiescent current, designed in a CMOS 0.35um/5V technology. The circuit relies on strong inversion operation, and the “inverse function”, achieving first order temperature compensation. Simulation results indicate 20ppm/deg.C between −40deg.C to 125deg.C, 6uA quiescent current and 2.8V minimum supply voltage.
In this paper, the design of a wideband LNA employing simultaneously noise cancellation and a linearisation technique is presented. The designed LNA consists of a cross-coupled common-gate topology for wideband matching and noise cancellation. Also, a linearisation technique is used in order to cancel out third order nonlinearities. The proposed LNA is designed in a 130 nm CMOS technology. It has...
This paper analyzes two dual-motor fault-tolerant topologies. The first one supplies independently both machines while the second one connects them in series for reducing the number of transistors. For a given DC-link voltage, the converter component sizing is based on the peak current obtained in the normal and degraded modes.
Power amplifiers providing an output current of high precision, high bandwidth and low distortion are required in different fields like magnetic resonance imaging or motion control systems for semiconductor production processes. This paper analyzes different power stage implementations of switched-mode (Class-D) amplifiers intended for such applications. They are preferred to linear or hybrid solutions...
There exists a fundamental limit in improving the phase noise performance of LC-tank oscillators. Impediments to reach this limit are first discussed, and then a clipping LC VCO topology based on dual tank is presented to mitigate them. This topology can approach within 3 dB of the maximum thermodynamically achievable figure-of-merit (FoM) limit. Compared to conventional class-B/C/D/F oscillators,...
This work presents a family of rad-hard ADCs with flash architecture for space applications. The converters, featuring from 4 to 8-Bit at 10MS/s, have been developed using rad-hardening techniques at architecture, circuit and layout levels. The 4-Bit ADC has been integrated in two standard CMOS 0.18-μm technologies by TowerJazz and XFAB. The prototypes have been tested under Co-60 and showed same...
In the research of low power VLSI circuits, the use and implementation of Transmission Gate Based MUX-Latches for serial link interfaces has gained more attention at the gate level design. Multiplexer-latches (MUX-Latches) possess the logic function of combinational circuits and storing capacity of sequential circuits. By using pipeline topology with Transmission Gate MUX-Latch, many latch gates for...
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