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This paper presents a new topology of High Instantaneous Power Impulse Converter (HIPIC). HIPIC at average power of kilowatts is able to generate very short impulses (tens of microseconds) to reach instantaneous high power in megawatt range. The new topology is composed of step-down converters, H-bridge converter and switched capacitor converter, what allows to obtain the output current impulses with...
One step ahead optimal Model Predictive Control (MPC) has been developed and demonstrated by simulation for current control in various — frequently used power converters, namely, 2 level, 3 level, matrix (MxC) and Vienna converters. The universal m ∗ n power converter with (m) inputs and (n) outputs was modeled by switching matrix whose elements define on/off states of power devices. To allow modeling...
This paper deals with a Sub-Hexagonal Centre PWM (SHCPWM) with variable switching sequence for a topology based on cascaded connection of two converters, so called dual inverter. The SHCPWM is enhanced to consider the last IGBT switching state representing the previous space vector and to balance and reduce power losses among the transistors. The proposed method is compared with the known SHCPWM with...
The paper deals with design and analysis of a variable-gain amplifier (VGA) working with a very low supply voltage, which is targeted for low-power applications. The proposed amplifier was designed using the bulk-driven approach, which is suitable for ultra-low voltage circuits. Since the power supply voltage is less than 0.6 V, there is no risk of latchup that is usually the main drawback of bulk-driven...
In this paper we show that the area optimization of STT-MRAM bitcells can deliver a substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is adopted. Indeed, the increase in the bitcell area enables the reduction in the write energy consumed by the bitcells at the expense of the energy of peripheral circuits, when lowering the supply voltage. The proposed approach...
The design of an ultra-low voltage CMOS wideband LNA topology operating under a 0.6 V power supply with high gain and high IP2 is presented in this paper. The circuit performance is targeted towards use in direct conversion receivers, where a high IP2 is required. The LNA operates in sub-1 GHz applications reaching frequencies as low as 50 MHz, as it is required by IEEE 802.22 standard. The topology...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology...
Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel...
Despite their substantial power savings, voltage scaling design increases the concern about sensitivity to manufacturing process and operating conditions variations. These can induce significant delay changes in fabricated circuits. An elegant approach to cope with these issues is to employ quasi delay-insensitive asynchronous design styles, which allow relaxing timing assumptions, enabling simpler...
This paper addresses the high-volume production test problem for millimeter-wave (mm-Wave) circuits. Bit error rate testing is the only feasible solution nowadays for mm-Wave transceivers, but is extremely costly and challenging to be implemented in high-volume production test floors. The lack of alternative solutions is due to the difficulty in extracting off-chip and processing mm-Wave frequencies...
In this paper, conditional push pull pulsed latch (CPPPL) is designed using Tanner tool. This latch is compared with other existing flip-flops. Total 12 flip-flops are compared with CPPPL which belong to different logic styles. Comparison is done through various parameters like energy, delay. From comparative analysis, it is found that CPPPL is efficient for balanced ED applications.
A constant-gm, rail-to-rail operational amplifier circuit topology is presented in this paper. The amplifier input stage is realized using single NMOS pair at 0.13μm bulk-CMOS process technology. The overall gain variation is within the range of ±2.338% for the rail-to-rail common mode input range. The proposed design is able to reject the common mode input response with 115dB of common mode rejection...
Design of variable-gain amplifier (VGA), based on fully differential operational amplifier is presented. The proposed VGA topology was verified through simulations and analysis of main circuit parameters. The VGA is designed in 0.35 μm CMOS technology using Cadence environment and BSIM3 family of models. Designed circuit works with the power supply of 3.3 V. The simulation results show that gain bandwidth...
In this paper, a variable gain amplifier designed in 130 nm CMOS technology is presented. The proposed amplifier is based on the bulk-driven approach, which brings a possibility to operate with low supply voltage (i.e. 0.6 V). Since the supply voltage of only 0.6 V is used for the amplifier to operate, there is no latchup risk that usually represents the main drawback of the bulk-diven approach. As...
A new scheme of a step-up converter with very high voltage gain is analyzed in this paper. The scheme is based on the combination of the switched-coupled-inductor boost converter and the diode-capacitor Cockoft-Walton multiplier. The scheme provides a soft commutation of the switch and the diodes. The paper analyzes the main modes of operation and obtained the formulas for determining the DC voltage...
In this paper, the main reason why AC electricity was accepted as the form of choice for the modern electric power system is the magnetic transformer. The inability to conveniently change voltage levels became one of the major drawbacks of Edison's early DC system concept. The DC transformer can be a device that, like its AC counterpart, provides lossless transfer of energy between circuits at different...
With the shrinking technology, new systems are designed that are miniature in size and perform faster operations. Adder is a basic circuit used for the purpose of addition. In a cascade design, the output of one circuit acts as an input for the other, so delay in the propagation of the carry generated while addition is major issue in the design of adders. When the circuit is designed with any other...
This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis,...
Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts...
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