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This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth)...
A constant-gm, rail-to-rail operational amplifier circuit topology is presented in this paper. The amplifier input stage is realized using single NMOS pair at 0.13μm bulk-CMOS process technology. The overall gain variation is within the range of ±2.338% for the rail-to-rail common mode input range. The proposed design is able to reject the common mode input response with 115dB of common mode rejection...
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