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This paper presents a power and performance multi-objective Tabu Search based technique for designing application-specific Network-on-Chip architectures. The topology generation approach uses an automated technique to incorporate floorplan information and attain accurate values for wirelength and area. The method also takes dynamic effects such as contention into account, allowing performance constraints...
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, enabling the design of highly integrated chips with many cores and a complex interconnect fabric, often a network on chip (NoC). Particularly problematic is the case when the accumulation of permanent hardware faults leads to...
This paper proposes a new dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip design. It simplifies the router design as well. It results in significant saving in the energy consumed by the network. For uniform traffic, the saving is as high as 63%. It offers the flexibility of designing routers of different sizes for mapping of applications.
Network on chip (NoC) is an effective solution to complex on-chip communication problem. The mesh topology is one of the most popular NoC. It has completely regular topology which can be implemented easily, but the communication delay between remote nodes is large. In this paper, we propose an improved topology called Tmesh, which is based on the standard mesh network by inserting four long links...
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding,...
In this paper, we design a topology-agnostic adaptive routing algorithm for application-specific in routing table based NoC routers. The basic idea relies on using SCC(Strongly Connected Component) based methodology, which can be done in polynomial time, to guarantee deadlock free and using mean packets arrival rate on the paths to solve the problem of paths diversity. The efficiency of the proposed...
In this paper, we investigate how the need for static analysis of data flowing through Networks-on-Chip in many-core and SoC systems may be eliminated, yet still allow network optimisations to improve runtime behaviour. Our approach is to replace a priori static analysis with run-time optimisations, taking place in the network itself. To do this, we introduce our self-optimising NoC topology: Skip-links,...
This paper presents a novel application mapping strategy onto the mesh topology for Network-on-Chip (NoC) design. Compared to the previously published works, this paper uses the approach of Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the topology using another heuristic algorithm. An iterative improvement...
The 2D mesh network on chip (NOC) is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the long distance traffic may suffer from high transmission latency. In this paper, we propose an improved design called the star-type architecture in which the long distance traffic is allowed to traverse an additional second-level mesh. Simulation results...
The Network-on-Chip (NoC) synthesis problem consists in generating NoC topology to guarantee system design objectives such as: system performance and area. A novel multi-objective NoC synthesis solver is proposed to design application specific NoC of multi-stage topology. Based on NSGAII, a multi-objective genetic algorithm, the solver aims to supply multi-objective Pareto solutions set for the multiple...
In this paper we make the design, the simulation and the implementation of a NoC (Network on Chip) 2-ary 4-fly in order to evaluate the speed up of an application with different NoC sizes. For the conception of the NoC, we use the tool NoCcompiler from Arteris Company. To test the performance of this NoC we integrate it as an IP (Intellectual Property) into an EDK project where masters are 16 Microblazes...
Asynchronous switching is proposed to achieve low power Network on Chip. Asynchronous switching reduces the power dissipation of the network if the activity factor of the data transfer between two ports αd is less than A αc + B αclk. Closed form expressions for power dissipation of Octagon topology are provided for both synchronous and asynchronous switching. The area of the asynchronous switch is...
The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations...
We propose a new custom Network-on-Chip (NoC) topology synthesis methodology consisting of floor planning, routers assignment, and routing paths calculation steps. The proposed heuristic methodology integrates fast algorithms based on the B*-tree representation for floor planning, on bipartite matching for the routers assignment step, and on multi commodity flow for congestion minimization for the...
Combining the benefits of 3D IC and Network-on-Chip (NoC) schemes, provides a significant performance gain for 3D stacked architectures. In recent years, Through-Silicon-Via (TSV), employed for inter-layer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient inter-layer communication across multiple stacked layers. However, the area overhead...
The growing size of Multi-Processor Systems-on-Chip (MP-SoC) calls for Networks-on-Chip (NoC) which scale with the increasing number of modules attached to them. Though current, 2D-mesh based NoCs scale linearly with the number of modules attached to them, their performance in terms of achievable throughput under typical traffic scenarios degrades. Clustered, hierarchical 2D-mesh NoCs may provide...
Network-on-Chip (NoC) is the most promising on-chip-interconnection scheme for multi-core processors. In this paper, we propose a novel NoC architecture called Stargon, which is inspired by the Spidergon. A simulation model has been developed to evaluate our architecture. We study the effect of the number of nodes, buffer depth and message length on the performance, and shows that at any situation...
This paper reviews Network-on-Chip architectures with prioritization of selected data streams targeting runtime reconfigurable manycore systems. The common idea of these architectures is to minimize the latency of selected packet transmissions by either bypassing or parallelizing processing stages in routers or by using dedicated links bypassing complete routers. Potential classes of selected data...
Network-on-Chip (NoC) has emerged as a solution for communication framework for high-performance nanoscale architecture. One important aspect, in addition to deadlock-free routing, is low power consumption. In view of varied communication requirements, application specific SoC design is increasingly important. Customized NoC architectures are more suitable for a particular application, and do not...
To continue the growth of the number of transistors on a chip, the 3D IC practice, where multiple silicon layers are stacked vertically, is emerging as a revolutionary technology. Partitioning a larger die into smaller segments and then stacking them in a 3D integration can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible...
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