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Model-based mutation testing (MBMT) is a promising testing methodology that relies on a model of the system under test (SUT) to create test cases. Hence, MBMT is a so-called black-box testing approach. It also is fault based, as it creates test cases that are guaranteed to reveal certain faults: after inserting a fault into the model of the SUT, it looks for a test case revealing this fault. This...
A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem...
The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as...
Oscillation test methodology (OTM) has been very effective in detecting physical defects such as open, shorts and bridging defects in low-voltage CMOS VLSI analog and mixed signal circuits. This paper discusses the OTM for low voltage two-stage operational amplifier using N-well 1μm CMOS technology with high fault coverage and minimum area overhead. Five bridging faults and one open fault have been...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
Digital systems have numerous advantages over analog systems including robustness, resiliency against operational variations. However, one of the most popular hardware security primitive, PUF, has been an analog component. In this paper, we propose the concept of digital PUF where the core idea is to intentionally use high-risk synthesis to induce defects in circuits. Due to the effect of process...
Modern microprocessor-based relays are designed to provide robust and reliable protection even with disruptions in the dc supply, dc control circuits, or interconnected communications system. Noisy battery voltage supplies, interruptions in the dc supply, and communications interference are just a few of the challenges that relays encounter. This paper provides field cases that investigate protection...
This paper is part two of the subject title and identifies some of the developing issues in testing what has here to fore been well understood protection elements we commonly used in designing modern protection systems. The core issue is the complexity of today's combined protection element scheme logic that enables these “understood” protection elements to function more securely and reliably - but...
Thyristor functioning as Arc Eliminator (AE) is presented in this paper, in order to protect low voltage devices such as circuit breakers from damage caused by arc fault. The AE operating mechanism is firstly illustrated, AE is usually working as an active standalone device together with other existing switchgears. The reason of choosing thyristor as AE is mainly because of its fast speed and relatively...
An approach to test application called transparent scan provides an opportunity to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The conventional methodology suffers from problems such as high power consumption, less quality results both in terms of pattern count and fault coverage...
Nowadays integrated circuits (ICs) lose its integrity because aged ICs are being recycled in the new products instead of fresh ICs. Replacing ICs potentially impacts the security and reliability of the electronic systems bound for military, financial and other critical applications. It is important to distinguish the aged ICs from the unused ones. The term aging implies the duration of IC in constant...
This paper proposes a novel idea for incorporating dual threshold voltage for Bit swapping LFSR (BS-LFSR) in order to obtain highly power efficient pattern generators for built in self-test (BIST) based VLSI architecture. BIST is a hardware entity, which is capable of testing the circuit during manufacturing as well as in situ conditions. It make use of different types of random generators for test...
The network-on-chip has become an emerging research area in the fields of system on chips, embedded systems, integrated circuits design, etc. with the rapid advancement of technologies. The introduction of multi-core chips has in addition made researches in the area ever significant and is growing to facilitate high demand of bandwidth via core utilization and need of scalable interconnection fabrics...
Cryptographic ICs are facing a serious threat of fault injection attacks. However, the security test nowadays is still sample test instead of volume test, exploiting workload statistics and experiences as qualitative indexes. This paper proposes a design for test method, to facilitate fast and automatic security test of cryptographic ICs. First we identify the sensitive registers crucial to the fault...
With the increasing number of Electric Vehicles (EV) in this age, the power system is facing huge challenges of the high penetration rates of EVs charging stations. Therefore, a technical study of the impact of EVs charging on the distribution system is required. This paper is applied with PSCAD software and aimed to analyzing the Total Harmonic Distortion (THD) brought by Electric Vehicles charging...
This paper proposes the use of parameterised FPGA configurations for a new test set generation approach. The time-consuming problem of test set generation aims at finding the right input values to fully test an ASIC design. Since well-known methods for test set generation such as fault simulation techniques have become impractical to use due to their speed limitations, FPGAs have been used in order...
Structural tests provide high defect coverage by considering the low-level circuit details. Functional test provides a faster test with reduced test patterns and does not imply additional hardware overhead. However, it lacks a quantitative measure of structural fault coverage. This paper fills this gap by presenting a satisfiability based method to generate functional test patterns while considering...
An non-volatile logic (NVL) -based system chip uses non-volatile storage elements to backup working state of volatile storage elements in sleep mode such that the power of chip can be turned off and zero standby power can be achieved. Since an NVL-based system chip consists of logic circuits and non-volatile storage elements, tests for logic circuits only and for non-volatile memories only are not...
This paper shows that existing delay-based testing techniques for power gating exhibit fault coverage loss due to unconsidered delays introduced by the structure of the virtual voltage power-distribution-network (VPDN). To restore this loss, which could reach up to 70.3% on stuck-open faults, we propose a design-for-testability (DFT) logic that considers the impact of VPDN on fault coverage in order...
Pre-bond testing of silicon interposer is difficult due to the large number of nets to be tested and small number of test access ports. Recently, it was proposed to include a test interposer that is contacted with the interposer under test in the testing process. Combining these two interposers provides access to nets that are not normally accessible. Previous synthesis method for test interposer...
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