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Power distribution equipment is the backbone of any Industrial process infrastructure. Safety and reliability are the two most important criteria in the proper functioning of the power distribution system. Low voltage switchgear is an important part of power distribution. Minimizing arcing faults in the switchgear is of utmost importance to enable a safe environment. Arcing faults increase the temperatures...
Diagnosis of each failed part requires the failed data captured on the test equipment. However, due to memory limitations on the tester, one often cannot store all the failed data for every chip tested. Consequently, truncated failure logs are used instead of complete logs for each part. Such truncation of the failure logs can result in very long turn-around times for diagnosis because important failure...
In this paper we consider detection of faults in CMOS cells that are more complex than primitive gates. We derive a single set of tests based on functional description of the cells. The tests derived, if applied, detect multiple stuck-at faults, multiple transistor stuck-open faults, cross wire open faults, delay faults and bridging faults between inputs of the cell, in any implementation of the cell...
Defects in TSVs due to fabrication steps decrease the yield and reliability of 3D stacked ICs, hence these defects need to be screened early in the manufacturing flow. We propose a non-invasive method for pre-bond TSV test and diagnosis that does not require TSV probing. We use open TSVs as capacitive loads of their driving gates and measure the propagation delay by means of ring oscillators. Defects...
TSVs can be fabricated with pitch of only tens of μm, and smaller. They can be densely distributed as inter-die interconnect in 3D ICs. However, the huge mismatch between the probe technology, such as the pitch of probe head and the capacity of probe card, and the TSV fabrication technology leads to an insufficient probe on TSV tips. In this paper, we present a novel TSV probing technique that can...
The paper presents a data-mining based comprehensive protection scheme for micro-grid using decision tree. The proposed scheme pre-processes the current and voltage signals at both ends of the faulted feeder using discrete Fourier transform (DFT) and compute the differential features, which are used to build two decision trees (DTs) for the final relaying decision. The differential features between...
Design-for-testability (DFT) reduces the test complexity of sequential register-transfer-level (RTL) circuits. Only enhanced scan technique from the scan based approaches guarantee two-pattern testability with a large area and test time overhead. This paper proposes a path delay DFT technique for functional RTL circuits. Data paths are modified into hierarchical single-port-change (SPC) two-pattern...
In this paper a method is presented to address the automatic testing of analog ICs. Based on Design-for-Testability building blocks offering extra controllability and extra observability, a test infrastructure is generated for a targeted circuit. The selection of the extra blocks and their insertion into the circuit is done automaticaly by a proposed optimization algorithm. Adopting a defect-oriented...
Built-in self-repair (BISR) approach utilized mostly in regular structures of memory cores has been a promising approach to increase the reliability of any type of integrated circuit. BISR considers spare blocks which in the case of a fault occurrence are used to replace defected circuit parts. A new fault detection and repair procedure with a generic BISR architecture for logic cores is presented...
The description of equipment and methods used for conducting ionizing radiation Accelerated Life Testing (ALT) of programmable hardware, especially Field Programmable Gate Arrays (FPGA) at the cyclotron is introduced. Methodology of testing and Single Event Effects (SEE) detection and online monitoring is described together with some results of testing several SRAM and Flash based FPGAs. In the course...
In this work we present a novel fault-tolerant circuits design method. It combines time and area redundancy to achieve error-correction abilities similar to a triple-modular redundancy (TMR) and the area-overhead close to a duplex system. New logic gates design allowing a complete stuck-at fault testability will be presented. Our method allows to test combinational parts of the circuit using a universal...
In today's VLSI world, the designers concentrate on low power design, neglecting the test methodology. Defining low power test methodology is the need of the day. In this paper, Microcode based Asynchronous P-MBIST is implemented, measured and compared with similar feature Synchronous PMBIST. The implemented core has given Power, Area advantage of 95.44%, 23.95% respectively but with increased Timing...
Reliability of digital microfluidic biochips (DMFB) emerges to be a critical issue, as they are becoming a popular alternative for laboratory experiments like DNA analysis, immunoassays and safety critical clinical diagnostics. To improve DMFB reliability, the key is to know the possible points of failure of its electrode cells. In this paper, a novel test methodology is introduced to monitor the...
3D IC using Through Silicon Via (TSV) is a promising technology for next generation of integrated circuits. Manufacturing TSV defects like voids and pinholes have to be detected at the test phase to ensure fault free ICs. In this paper a contactless probe utilizing capacitive coupling is presented. The proposed method eliminates the impact of direct probing on TSV and supports the high-density and...
Since VLSI technology has become ubiquitous in today's world, this field is a prime candidate for power reduction. Tremendous growth in chip density and reduction in dimensions contribute to an escalation in clock rate. Delay faults are detected using at-speed scan testing. This paper proposes a novel method to achieve power reduction during scan test by using x-filling. In this paper, ISCAS′89 benchmark...
Boundary scan test technology with its unique “virtual probe” characteristic provides a powerful means to solve the difficult problem of high density integrated test system components. It introduces the development of a more general boundary scan test system based on EDIF (Electronic Design Interchange Format). The hardware of the system is based on USB bus, including the PC, USB driver interface,...
This paper will present the design of SCE's Smart Grid Test Facility (SGTF) and equipment test. This facility can be used to test, demonstrate, and validate utility distribution equipment performance before, during, and/or after their installation in the grid. This test facility's voltage, frequency, real power, and reactive power will be completely controlled where the equipment's automation, protection,...
While working with designers and DFT engineers in companies evaluating an “industrial-strength” analog fault simulator, it became apparent that intuition and theory often differ regarding random sampling of defects to simulate. This paper explores these differences. In one case, it was hoped that simulating more defects would increase the estimated coverage. In a second case, it was assumed that pre-simulation...
Power distribution equipment is the backbone of any Industrial process infrastructure. Safety and reliability are the two most important criteria in the proper functioning of the power distribution system. Low voltage switchgear is an important part of power distribution. Minimizing arcing faults in the switchgear is of utmost importance to enable a safe environment. Arcing faults increase the temperatures...
With the rapid advancements of deep submicron and nano technologies the dimension of a chip is ever shrinking. With continuous shrinking of chip dimensions, immense interconnects are associated on a die to satisfy high bandwidth requirements and make a network-on-chip (NoC) architecture prone to large number of interconnect faults. Therefore the reliability becomes a crucial issue for the communicating...
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