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The cross-point array architecture with resistive synaptic devices has been proposed for on-chip implementation of weighted sum and weight update in the training process of learning algorithms. However, the non-ideal properties of the synaptic devices available today, such as the nonlinearity in weight update, limited ON/OFF range and device variations, can potentially hamper the learning accuracy...
The present day video coding standards such as MPEG and H.264 are mainly used for broadcast applications, where the encoder is more complex than the decoder. However, for applications such as low power surveillance networks and wireless video cameras, where there is a dearth of hardware at the encoder, the encoder needs to be simpler, but the decoder can be complex. Distributed Video Coding (DVC)...
The design of multi-Gbps LDPC decoder has become a hot topic in recent years as the demand of transformation towards 5G. An energy efficient 18Gbps LDPC decoder based on LDPC ASIP with half layer paralleled architecture is proposed. The feasibility of the design is proven by its demonstrator silicon in 28nm CMOS technology, with a record energy efficiency of 18.4 pJ/decoded bit and area efficiency...
In classifying images, scenes or objects, the most popular approach is based on the features extraction-coding-pooling framework allowing to generate discriminative and robust image representations from densely extracted local patches, mainly some SIFT/HOG ones. The majority of the latest research is focused on how to improve successfully these coding and pooling parts. In this work, we show that...
This paper proposes a new adaptive sharpening filter based on guided image filter and improves HEVC's in-loop filter architecture by embedding sharpening filter between deblocking filter and SAO. The proposed algorithm classifies pixels of a frame into several groups according to uniform quantization of each pixel's Sum-Modified-Laplacian value and assigns identical optimal filtering parameters to...
In order to enable a system which offers compatibility with currently existing H.264/AVC based systems, 3D functionality, and a low overall bitrate, a multiview H.264/HEVC hybrid architecture was proposed in the context of 3D applications and standardization. This paper presents an algorithm to reduce the complexity of this multiview hybrid architecture by reducing the encoding complexity of the HEVC...
We apply belief propagation to a Bayesian bipartite graph composed of discrete independent hidden variables and discrete visible variables. The network is the Discrete counterpart of Independent Component Analysis (DICA) and it is manipulated in a factor graph form for inference and learning. A full set of simulations is reported for character images from the MNIST dataset. The results show that the...
Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architectures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed...
In this paper, a small area hardware architecture for deblocking filter of HEVC is proposed. To achieve high throughput and small area, an efficient processing order based on a CTU-based pipeline is proposed. The proposed architecture is synthesized in ALTERA Cyclone V 28nm process FPGA with 28.7K gate counts. The simulation result shows that the proposed architecture achieves an area reduction of...
This paper presents a highly parallel motion estimation architecture for High Efficiency Video Coding (HEVC) encoder. The proposed architecture has 16 processing units operating in parallel to calculate the sum of absolute difference values of all possible variable prediction block sizes. Hence, it calculates the bit cost regarding every partition in order to find the best matching candidate in terms...
Multiplication is an important mathematical operation in many microprocessor architectures. And, multipliers have evolved dramaticlly after the late 1970s and have gone through tremendous changes with an aim of reducing the area and delay. This paper presents and an extension to Booth-3 multiplication architecture by implementing the partial product matrix in redundant form. It is anticipated that...
This article is concerned with the acquisition of mul-timodal integration capacities by learning algorithms. Humans seem to perform statistically optimal fusion, and this ability may be gradually learned from experience. In order to stress the advantage of learning approaches in contrast to hand-coded models, we propose a generative-discriminative learning architecture that avoids simplifying assumptions...
The added encoding efficiency and visual quality that is offered by the latest HEVC standard is mostly attained at the cost of a significant increase of the computational complexity at both the encoder and decoder. However, such added complexity greatly compromises the implementation of this standard in computational and energy constrained devices, including embedded systems, mobile and battery supplied...
We present a framework based on constraint satisfaction that adds self-integration capabilities to component-based embedded systems by identifying correct compositions of the desired components and their dependencies. This not only allows autonomous integration of additional functionality but can also be extended to ensure that the new configuration does not violate any extra-functional requirements,...
The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial...
The residue number system t = {2n -- 1, 2n, 2n + 1} has been extensively studied towards perfection in realization of efficient parallel prefix modular adders, with (3 + 2log n ?G) latency. Many applications, such as digital signal processing require fast modular operations. However, relying only on t limits the magnitude of n, and accordingly the dynamic range. Therefore, additional mutually prime...
This paper shows a novel concept of the Reed Solomon (RS) codec IP generator for produce ten kinds of RS codec including RS(28,24), RS(32,28), RS(36,22), RS(72,64), RS(182,172), RS(204,188), RS(207,187), RS(208,192) [1], RS(255,223) [2] and RS(255,239) for targeting various communication standards and systems which use Reed Solomon (RS) codes. The RS codec IP generator will perform the hardware design...
The emerging computational complexities arises the need of fast multiplication unit. The importance of multiplication in various applications necessitates improvement in its design so as to obtain the multiplication result efficiently. Multiplication operation can be improved by reducing the number of partial products to be added and by enhancing the adder unit for obtaining sum. The number of partial...
This paper proposes an FPGA architecture for the 1-D forward integer transform of the High Efficiency Video Coding (HEVC), which is the latest video coding standard. The work presents a novel technique which makes the architecture able to compute transform of flexible input combinations. The architecture can support all transform sizes i.e. 4×4, 8×8, 16×16, and 32×32, and all possible input combinations...
A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of...
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