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This paper proposes an FPGA architecture for the 1-D forward integer transform of the High Efficiency Video Coding (HEVC), which is the latest video coding standard. The work presents a novel technique which makes the architecture able to compute transform of flexible input combinations. The architecture can support all transform sizes i.e. 4×4, 8×8, 16×16, and 32×32, and all possible input combinations...
The capacitor-less LDO regulator with slew-rate enhancement disabling scheme has been introduced and postlayout simulated in 2P4M 0.35-μm CMOS process. The output voltage can be adjusted on-the-fly from 0.9 to 1.6 V with minimum supply voltage of 1.6 V (0.1 V dropout). The regulator consumes less than 78 μA quiescent current and can supply 0– 100 mA load with 5 μs settling time.
Teamwork assessment by peers in small groups could be affected by personal relationships. This paper presented a system of teamwork assessments for a postgraduate course in a Thai university that integrated the collaborative learning and hand-on group projects as the means to deliver the desired outcome. Students found assessments quite suitable in assessing the teamwork and sufficiently detailed...
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