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The matrix keyboard is taken as the basic input device of MCU or embedded systems. For traditional matrix keyboard, the number of interface signal lines connected to the MCU will rapidly increase with the rise of the number of keys. And it uses row scanning to get key values in software. But this situation is not suitable for MCU (Micro-programmed Control Unit) or embedded chips which have limited...
QDI-model-based asynchronous circuits which contain differential domino logic (DDL) circuits are promising implementation against random delay variations. A physical DDL cell can represent all the family functions without extra gates since it is based on the dual-rail encoding. This paper proposes a physical DDL library which only contains 12 cells and three logical synthesis libraries for this physical...
In this paper, we study the problem of solving hard propositional satisfiability problem in Cloud or computing grid, which is honest-but-curious. We propose an approach to preserve input and output privacy based on CNF obfuscation, and present obfuscation algorithm and its corresponding solution recovery algorithm. By obfuscation, the CNF formula is transformed into another formula, with different...
All-IP network in Indonesia are still few in number. It is estimated that more than 5 years from now there are a combination of non-IP networks and all-IP network. At this time, an international VoIP service in Indonesia is given by the regulated and unregulated providers. The regulation of VoIP services are included in government regulation number KM.23.2002 about internet telephony for public use...
This paper studies the Parlay gateway traffic overload control problems in electric power communication networks. A traffic overload control algorithm with energy efficiency is proposed to solve it. Firstly, the fairness and effectiveness of the Parlay gateway is analyzed. Then we can establish the constraints about fairness and effectiveness. The electric power communication network energy efficiency...
Reversible logic has received great importance in the recent years because of its in-cogitative feature of reduction in power dissipation which is the key requirement in low power digital designs. It has wide applications in advanced computing, low power CMOS design, optical information processing, DNA computing, bio information, quantum computing and nanotechnology. In this paper a new reversible...
SAT solvers have been used as ATPG solution due to the advantage of transforming the circuit to a mathematical problem that can quickly be solved rather than using traditional circuit based approach. In this paper, we present a novel technique for dynamically compacting the test vector set in SAT-based ATPG as it searches for individual vectors, hence giving out fewer patterns that cover more faults...
Scaling supply voltage to near-threshold is a very effective approach in reducing the energy consumption of computer systems. However, executing below the safe operation margin of supply voltage introduces high number of persistent failures, especially in memory structures. Thus, it is essential to provide reliability schemes to tolerate these persistent failures in the memory structures. In this...
It is strongly demanded to reduce power consumption in wiring such as data bus of Complementary Metal Oxide Semiconductor (CMOS) logic circuits, especially used in mobile devices. The power consumption in CMOS is proportional to transition rate between ‘0’ and ‘1’ of each bit, and a lot of methods to reduce the transition rate have been proposed. On the other hand, in band-limited data, such as audio...
This paper proposes an architecture for structured low density parity check encoder. The proposed architecture supports the limitation of input/output pins of field programmable gate array using division of information bits. The division of information bits generates latency of encoding. The proposed architecture does not store the required matrix for bit-wise multiplication and does not use cyclic...
This paper focuses on geostationary satellite scenarios and investigates the performance of several Transmission Control Protocol (TCP) variants in a novel Performance Enhancing Proxy (PEP) architecture solution, whose added value is the use of network coding beneath the transport layer. Comparison of TCP New-Reno, Vegas, Scalable, CUBIC, Hybla, and HTCP and the cases where these transport protocols...
This paper presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins...
SAT solvers have been at the forefront of ATPG solutions due to the inherent advantages of transforming the circuit to a mathematical problem. One that can quickly be solved by tried and true algorithms, rather than using traditional circuit based solutions. Unfortunately while this speedup may find a test vector for a specific fault to be detected, the number of test vectors detected for the entire...
Synthesis tools for high-performance VLSI designs employ aggressive logic optimization techniques in order to meet physical requirements such as area and cycle time. During these optimizations, the original structure of the design, which is usually written in a hardware description language (HDL), is lost. It is difficult, and often impossible, to relate signals after synthesis to the original signals...
Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to Bias Temperature Instability and Hot Carrier Injection. As a result, device delays increase over time reducing the Mean Time To Failure (MTTF) of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically...
Motivated by its promising applications e.g. for database search or factorization, significant progress has been made in the development of automated design methods for quantum circuits. But in order to keep up with recent physical developments in this domain, new technological constraints have to be considered. Limited interaction distance between gate qubits is one of the most common of these constraints...
Bose-Chaudhuri-Hocquenghem (BCH) coding based on chip communication network is proposed to achieve optimal Energy-Perfomabilty trade-off. The proposed encoding and decoding scheme is applied to Butterfly-fat-tree (BFT) architecture. The proposed design improves Perform-ability range in comparison with conventional schemes while saving energy by 5%. BCH achieves high perform-ability (0.9) at high noise...
This paper presents a low-power FPGA that the supply voltage of each logic block autonomously changes to suit their deadlines. Dual-rail coding is used in FPGA datapaths to make data transfer time sensible in each pipeline stage. The deadline of the logic block in each pipeline stage is evaluated by comparing the data transfer time and the pipeline cycle time. When a low supply voltage does not violate...
For MeV gamma-ray Astronomy, we have developed an Electron Tracking Compton Camera (ETCC) as a next-generation MeV gamma-ray telescope. An ETCC consists of a three-dimensional electron tracker using a gaseous time projection chamber (TPC) and position-sensitive gamma-ray absorbers using pixel scintillator arrays (PSAs). We carried out the balloon borne experiment in 2006 with a small size ETCC and...
Simulation-based verification is still the state-of-the-art when checking the correctness of complex Systems-on-Chips. In particular, constraint-based simulation is popular, since here dedicated stimuli are generated which trigger certain corner-case behavior. However, to the best of our knowledge, only heuristic methods have been introduced so far. In this paper, we propose an approach that determines...
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