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The memristor device has emerged as the missing fourth fundamental circuit element after resistor, inductor and capacitor. Various implementations of memristors have been reported, with the one using a TiO2 layer sandwiched between two platinum electrodes considered to be most promising. Because of its very small feature sizes and low power consumption, it is projected to replace CMOS technology in...
This paper presents a new coding scheme that considerably increases the efficiency of the channel in multicast setting. Specifically, we study the scenario where three terminals exchange their messages via a satellite gateway. The main difference between the proposed scheme and conventional three-way relay channel is the use of joint channel and network coding. This allows three terminals to transmit...
This paper analyses the principle and effect of active laser high repetition frequency jamming in the semi-active laser guidance. According to existing decoding methods for active laser high repetition frequency jamming, a cascade way of multiple FPGAs is proposed and its principle and rule are introduced, especially, the cascade and codec synchronization methods are involved, providing a new thought...
As modern ASIC technologies suffer from substantial delay uncertainties, delay insensitive (DI) communication protocols are receiving increasing attention. Among these, the more energy-saving 2-phase protocols are most attractive. In the literature such protocols are widely covered already, with Level-Encoded-Dual-Rail (LEDR), Level-Encoded-Transition-Signalling (LETS) and Transition Encoding (TranEnc)...
Polar Codes can provably achieve the capacity of discrete memoryless channels. In order to make practical, it is necessary to propose efficient hardware decoder architectures. In this paper, the first hardware decoder architecture implementing the Soft-output CANcellation (SCAN) decoding algorithm, is presented. This decoder was implemented on Field Programmable Gate Array (FPGA) devices. The proposed...
Secure Write-Efficient Memory (WEM) was proposed in [11] to solve the endurance and the insecure deletion problems in flash memories. Information theoretical results, i.e., the achievable region and the secrecy rewriting capacity, have been obtained. In this work, a code construction for secure WEM is presented and it is optimal for a large family of secure WEM.
In this paper, a small area hardware architecture for deblocking filter of HEVC is proposed. To achieve high throughput and small area, an efficient processing order based on a CTU-based pipeline is proposed. The proposed architecture is synthesized in ALTERA Cyclone V 28nm process FPGA with 28.7K gate counts. The simulation result shows that the proposed architecture achieves an area reduction of...
The compact arithmetic units in stochastic computing can potentially lower the implementation cost with respect to silicon area and power consumption. In addition, stochastic computing provides inherent tolerance of transient errors at the cost of a less efficient signal encoding. In this paper, a novel FIR filter design using the stochastic approach based on multiplexers are proposed. The required...
The residue number system t = {2n -- 1, 2n, 2n + 1} has been extensively studied towards perfection in realization of efficient parallel prefix modular adders, with (3 + 2log n ?G) latency. Many applications, such as digital signal processing require fast modular operations. However, relying only on t limits the magnitude of n, and accordingly the dynamic range. Therefore, additional mutually prime...
As various types of Internets of Things (IoT) are deployed in a wide range of areas, the need arises to utilize various IoT resources dynamically to accomplish user tasks. We call this environment an urban-scale IoT environment, where various IoT resources that are necessary to accomplish user tasks are directly connected to each other via users' mobile devices, such as their smart phones. IoT resources...
Maximum Clique Problem (MCP) is one of the most important NP-hard problems in the area of soft computing and it has many real world applications in numerous fields ranging from coding theory to the determination of the structure of a protein molecule. Different heuristic, Meta heuristic and hybrid solution approaches have been applied to obtain the solution. In this paper, we demonstrate a Quantum-inspired...
This paper presents a hybrid multimode Bose Chaudhuri Hocquenghem (BCH) encoder for reducing the input length of Syndrome calculation (SC) based on re-encoding approach. In previous re-encoding approaches, a conventional BCH encoder with long generator polynomials is used as a remainder operator to reduce the input length of SC. However, the input length is still large since long polynomial is used...
Because of the rapid growth of air traffic, optimizing airport management is becoming necessary in order to improveairport's capacity and better align its resources to the received traffic. In this paper we study the assignment of the arriving aircrafts to the available gates using the fixed daily schedule. We introduce a new approach based on Genetic Algorithms (GA) to solve the gate assignment problem...
Security issue occupies an important part in all communication system and especially for new generation networks. Among these networks, we find Delay Tolerant Mobile Networks (DTMNs) which are a class of useful but challenging networks. Combining Network Coding (NC) and clustering for routing in such networks gives more efficiency and copes with routing reliability problem among large scale networks...
Hardware Trojan Horses (HTH) are a serious threat to semiconductor industry with significant economic impact. We introduced in [10] a method called “encoded circuit”, which both prevents and detects HTH. We achieved this goal using Linear Complementary Dual (LCD) codes. In this paper, we achieve a lower overhead and a better tunability by using a Linear Complementary Pair (LCP) of codes, which are...
Test generation algorithms considering unknown (X) values are pessimistic if standard n-valued logic algebras are used. This results in an overestimation of the number of signals with X-values and an underestimation of the fault coverage. In contrast, algorithms based on quantified Boolean formula (QBF), are accurate in presence of X-values but have limits with respect to runtime, scalability and...
This paper proposes a method of LFSR seed generation for deterministic and pseudo-random testing of static faults. The proposed method directly generate seeds by using ATPG and avoids unsuccessful encoding of conventional two-pass generation methods. The effectiveness of the proposed method is evaluated through experiments for several LFSRbased pseudo-random pattern generators. The quality of seeds...
This paper discusses the synthesis and implementation of various scheduling algorithms for Network-on-Chip communication. Traditionally these scheduling algorithms were implemented on ASIC platforms generally for shared bus based interconnection systems. In this paper we carry a comparative analysis by synthesizing and implementing various scheduling algorithms for configuring the crossbar in input...
In this paper an 8B/10B encoder and 10B/8B decoder is implemented which are widely used in high speed applications. In this paper we have used NAND/NOR gate instead of AND/OR gate used in earlier work. We calculated on-chip and hierarchy power for two frequencies (i.e. 20 MHz and 200 MHz) for both encoder and decoder using AND/OR gate and encoder and decoder using NAND/NOR gate. Using NAND/NOR gate...
Efficiently solving numerous relevant circuit satisfiability (CircuitSAT) problems becomes a crucial industrial topic as the design scale expands. In this topic, we are especially interested in: how to select the best setting of the Boolean satisfiability (SAT) solver based on sample problems, and what is the most useful conjunctive normal form (CNF) encoding for some particular designs and particular...
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