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As device scaling becomes increasingly difficult, 3D integration with through silicon via (TSV) has emerged as a viable solution for addressing the requisite bandwidth and power efficiency challenges. However, mechanical stresses induced by the TSVs must be controlled in the 3D flow in order to preserve the electrical integrity of front-end devices. Since copper filling material of the TSV could causes...
Alongside the intensive debate concerning the influence of hydrogen on NBTI we present several details which have received little or no attention in the past. We show experimental evidence that hydrogen does not only passivate interface traps but also positive oxide charges or border traps. Besides passivation, hydrogen increases the overall drift capability of a device under NBTS, thereby increasing...
The effect of stress concentration around Cu through-silicon via (TSV) on carrier mobility in typical metal oxide semiconductor field effect transistor (MOSFET) Si inversion layer is considered by using numerical finite element simulation in combination with piezoresistive equations. Carrier mobility changes along <100> or <110> channel directions are obtained for transistors...
Silicon (Si) IGBTs are widely used in railway traction converters. In the near future, Silicon Carbide (SiC) technology will push the limits of switching devices in the three directions: higher blocking voltage, higher operating temperature and higher switching speed. All in all, these large-gap components should improve the traction chain efficiency and the power-weight ratio. Thus, the topology...
Development of new wide band gap (WBG) power devices, and among them, of Silicon Carbide (SiC) power devices, has been an active field of research during the last years. Potential advantages SiC devices over their Si counterparts include a significantly higher breakdown field, higher operating temperatures as well as higher switching frequencies. However, manufacturing of SiC power devices is not...
In this paper we present a comparison of the EMI generated by a dc-dc boost converter, using silicon (Si) or silicon-carbide (SiC) diodes and/or MOSFET. EMI was compared using Si technology as reference. The comparison parameters were the switching times, and the conducted and radiated EMI. The paper shows that the use of SiC diode has great influence on the radiated EMI. The use of SiC MOSFET combined...
Silicon Carbide (SiC) devices and modules have been developed with high blocking voltages for Medium Voltage power electronics applications. Silicon devices do not exhibit higher blocking voltage capability due to its relatively low band gap energy compared to SiC counterparts. For the first time, 12kV SiC IGBTs have been fabricated. These devices exhibit excellent switching and static characteristics...
We investigate an efficient way to handle the SiGe/Si heterostructure in pMOS FDSOI devices. The electrostatic is studied using a self consistent 6-band k.p Schrodinger-Poisson solver. We show that the heterostructure can be efficiently treated using an analytical in-plane integration of the charge density based on the effective mass approximation dispersion relation. The shift of the threshold voltage...
The emerging Gallium-Nitride (GaN) based power transistors offers the potential to achieve higher efficiency and higher switching frequencies than possible with Silicon MOSFET's. This paper will discuss the GaN device characteristics, and based on this, the driving method will be discussed. Then a three-level driving method is proposed to overcome the high reverse conduction loss issue of the GaN...
The demand for exponential improvement in MOSFET performance versus cost has driven the Industry to miniaturize the die size thus maximizing the die density per square inch of wafer, and exploring breakthroughs in the device design and the wafer fabrication processes. The conventional planar Gate structure on top of the silicon surface is now being replaced by vertical gate micro structure inside...
FinFET provides needed relief to ICs from performance, power, and device variation predicaments. It also provides higher carrier mobility, especially at low voltage near the threshold voltage, giving promise to practical near-threshold circuits. Another new transistor conceived simultaneously with FinFET, UTB-SOI FET, is also entering production. Together they showed a new scaling path forward: scale...
The quasi-planar segmented-channel MOSFET (SegFET) design provides an evolutionary pathway for continued CMOS technology scaling, and can be fabricated using a conventional process flow starting with a corrugated substrate. It has been shown previously that the SegFET exhibits better short channel behavior compared to the conventional MOSFET. Recently, we have demonstrated further performance enhancement...
As MOSFET scaling has attained the 22 nm node, alternative concepts are intensively being investigated. The concept of the Tunneling Field Effect Transistor (TFET) is currently being explored as one of the device concepts most likely to enable energy efficient computation that, in addition, can potentially outperform the conventional MOSFET. We present a vertical device architecture grown with a solid...
We demonstrate for the first time that the high-k gate dielectric reliability is dramatically improved by replacing metal gate electrode with graphene gate electrode. The atomic-scale thickness and flexible nature of graphene completely eliminate mechanical stress in the high-k gate dielectric, resulting in significant reduction of trap generation in the high-k film. Almost all the electrical properties...
The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 µm × 30 µm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 µm × 30 µm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation...
This paper summarizes the electrostatics and performance of III–V field effect transistors including thin body planar MOSFETs, 3-D tri-gate MOSFETs, and Tunneling FETs (TFETs). The electrostatics of the III–V devices is shown to improve from thick body planar to thin body planar and then to 3-D tri-gate. Beyond the MOSFET structures, sub-threshold slope (SS) steeper than 60 mV/decade has been demonstrated...
The variation of saturation drain current (Id,sat), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of Id,sat is originated from Vth,sat and saturation velocity (Vsat), while the variation of Vth,sat comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that Vsat...
This paper reports InAs quantum-well (QW) MOSFETs with record transconductance (gm,max = 1.73 mS/µm) and high-frequency performance (fT = 245 GHz and fmax = 355 GHz) at Lg = 100 nm. This record performance is achieved by using a low Dit composite Al2O3/InP gate stack, optimized layer design and a high mobility InAs channel. This work is significant because it shows a possible III-V material pathway...
The pMOSFET device with a novel Si/Ge super-lattice (SL) channel is proposed in this work. Experimental results show that the electrical characteristics can be obviously improved by SL virtual substrate. The peak hole mobility of pMOSFET device with SL is enhanced to twice as high as that with Si one. The on-off ratio of Id-Vg curve is beyond 8 orders, and the EOT value of gate dielectric can be ∼...
In planar MOSFET, the optimization of finger length should be carried out with considering fT, fmax and flicker noise because the noise degradation at STI edge effect appears below 1µm. In FinFET, the optimization of not only finger length but also the distance between gate and source, drain contact region and fin pitch are necessary to reduce parasitic resistance and capacitance. According to our...
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