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The design of an ultra-wideband (UWB) CMOS receiver front-end that integrates a broadband single-ended low-noise amplifier (LNA) and a quadrature downconversion balun-mixer is presented. Noise-canceling technique is employed in the LNA to decouple input match from noise figure (NF). To be directly driven by the LNA, the balun-mixer has a single-ended input double-balanced topology. For low power consumption,...
In this paper, the sources of DC offset and the corresponding DC offset cancellation techniques are analyzed. A DC negative feedback technique based DC offset canceller (DOC) is designed in details and implemented by SMIC 0.18μm CMOS process. DC offset detector is an important part of DOC. In this paper, an on chip DC offset detection circuit is proposed for the DC negative feedback canceller which...
A wideband 1.1-1.7GHz low-noise amplifier (LNA) for dual-band global positioning system (GPS)receiver is presented.It is a single-ended amplifier with differential double-ended output. Input matching is extended to wide bandwidth using an input three-section band-pass Chebyshev filter. The LNA,integrated in SMIC 0.18μm CMOS process with a bandwidth of 1.1-1.7GHz, exhibits a power gain of more than...
This paper presents a design of high-speed flash analog-to-digital converter (ADC) in 0.13-μm CMOS technology for ultra wide band (UWB) receivers. The flash ADC is suitable for the high speed and low resolution application because of its fast speed and simple structure. In the ultra high speed situation, the track and hold amplifier and the comparator is the bottle neck for the whole ADC. In this...
This paper presents a L1 band low noise integrated global positioning system (GPS) receiver chip using 0.18-um CMOS technology. Dual-conversion with a low-IF architecture was used for this GPS receiver. The receiver is composed of LNA, down-conversion mixers, band pass filter, received signal strength indicator, variable gain amplifier, programmable gain amplifier, ADC, PLL frequency synthesizer and...
This paper presents a flexible timing circuit with 1.1ns delay resolution for energy detection IR-UWB receivers. Referenced at 900MHz input clock, the circuit generates multi-phased integration windows and reset signals that enable/disable the operation of analog blocks. The design is highly programmable, adapting the receiver to pulse level synchronization, symbol level synchronization, different...
Hidden bombs and abandoned military landmines buried in the afterwar field has become a severe threat to the society. A stand-off, high sensitive and portable explosive detection system is required to help this situation. Nuclear Quadrupole Resonance (NQR) detection technology has proven to be a highly effective solution for unambiguously detecting explosives, since NQR is an inherent characteristic...
This paper describes CMOS circuit design techniques for a limiting amplifier and received signal strength indicator (RSSI) circuits for the GPS receiver. The circuits in limiting amplifier and RSSI are all preudo differential to minimize the requirement of the supply voltage and be prepared against device mismatch. A folded diode load and folded cascade structure gain cell is introduced for each gain...
A single-chip broadband CMOS receiver front-end, integrating a low-noise amplifier (LNA), a correlator and a template pulse generator, was investigated in non-sinusoidal time-domain environment for possible use as a carrierless ultra-wideband (UWB) receiver front-end. Particularly, the CMOS LNA and the multiplier making up the core component of the correlator were designed, fabricated and tested to...
A new receiver front-end operating over the 3.1-4.8 and 6.3-7.9 GHz dual-band in the ultra-wideband (UWB) spectrum (3.1-10.6 GHz) was developed using a 0.18-μm CMOS process. The receiver front-end has a chip size of only 1.18 × 0.87 mm2 and exhibits conversion gains of 12.5-16.5 dB and 14.5-16 dB over the 3.1-4.8 GHz and 6.3-7.9 GHz bands, respectively. The measured input 1-dB compression points are...
This paper presents the design and implementation of a 6 Gbps clock and data recovery (CDR) system for Serial Advanced Technology Attachment (SATA) standard. The CDR incorporates half rate phase detector and is realized using a 2 loop PLL consisting of a coarse loop and a fine loop. Fast frequency acquisition is acquired through coarse loop and fine phase alignment is performed through a half rate...
This paper presents a new receiver circuit that is suitable for low-swing interconnect schemes in CMOS nanometer technologies. Compared to the conventional receiver, which utilizes a PMOS feedback transistor, the proposed configuration is based on an auxiliary cross-coupled structure, which provides significant reduction of the delay time and eliminates the short circuit current, during transitions...
A new ultra-wideband 0.18-μm CMOS sampling receiver frontend was developed. It includes a low-noise amplifier (LNA) and a sampler and achieves high gain, fast sampling, low noise figure, low power consumption, and enhanced RF-power efficiency. The LNA and sample-and-hold capacitor are switched using two synchronized strobes generated on-chip. Measured results show performance of 9 to 12 dB voltage...
A 60GHz CMOS multichannel wireless repeater, which converts digital data and millimeter-wave pulses without applying signal processing, is proposed for high-speed communication. A chip containing three repeaters operating at 60.48GHz, 62.64GHz and 64.8GHz frequency bands is fabricated using a 90nm CMOS process. Each channel has a 1Gbps data rate with power consumptions of 51mW and 116mW in the transmitter...
A 100Mb/s, 1.71mW DC-960MHz band impulse radio ultra-wideband (IR-UWB) receiver is developed in 1.2V 65nm CMOS. A novel auto- and cross-correlation based synchronization scheme is proposed to achieve 62.5ps step data synchronization with a 2-GHz 8-phase PLL clock generator. The developed UWB receiver with the proposed power- and area-efficient PLL achieves the low energy consumption of 17.1pJ/bit.
This paper presents the design of a DFE for a 2x blind ADC-based RX. The DFE is implemented in 65-nm CMOS along with a 2x blind CDR and ADC. Our measured results confirm 5Gb/s data recovery with BER less than 10-12 with a channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. Without the DFE, the BER exceeds 10-8.
A low-IF quadrature GPS receiver consisting of a VCO, mixer and variable gain LNA is implemented in 130 nm CMOS. Consuming 352 μW from a 250 mV supply, it has the lowest supply voltage for an integrated receiver reported to date. The measured noise figure is 7.2 dB with a gain of 42 dB at a 10 MHz IF frequency. At a 1 MHz offset, the VCO phase noise is -112.4 dBc/Hz, resulting in an FoM of 187.4 dBc/Hz.
This paper describes a new switching topology of a sampling mixer for SAW-less GPS (L1 band) receivers. The GPS receiver with the new mixer achieved NF 2.5dB and good blocking performance. In an alternative implementation, the mixer is stacked under a Quadrature VCO to reuse supply current. As a result, the current consumption of the GPS receiver is 11mA from 1.8V supply while maintaining blocking...
We present an integrated 900MHz receiver with 56.4dB conversion gain, 5dB NF, and -9.8dBm IIP3 using on-chip in-band feed-forward interference cancellation. The interference cancellation at baseband gives more than 13dB IIP3 improvement and makes operation from an ultra-low 0.6V supply possible. The direct-conversion receiver including baseband filters and polyphase LO filters and buffers consumes...
In this paper, a low-power broadband automatic-gain-control (AGC) amplifier targeted for use in the Square Kilometer Array (SKA) is presented. The AGC is composed of an input power-match circuit, a linear-in-dB output variable gain amplifier (VGA), a power detector (PD), an error amplifier, a comparator and a loop filter. The input stage is power matched to 100 Ω differential source impedance, achieves...
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