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This paper presents a new operational amplifier sharing technique for a continuous-time ΔΣ analog-to-digital converter (ADC). This technique saves power consumption by reducing the number of active elements in the modulator. Furthermore, the shared amplifier acts both as an adder and integrator in two different clock phases. The proposed technique also can be realized in a noise-coupled delta-sigma...
A low-IF quadrature GPS receiver consisting of a VCO, mixer and variable gain LNA is implemented in 130 nm CMOS. Consuming 352 μW from a 250 mV supply, it has the lowest supply voltage for an integrated receiver reported to date. The measured noise figure is 7.2 dB with a gain of 42 dB at a 10 MHz IF frequency. At a 1 MHz offset, the VCO phase noise is -112.4 dBc/Hz, resulting in an FoM of 187.4 dBc/Hz.
An ultra-low power transceiver for battery-free wireless sensor networks is presented. The receiver uses a modified super-regenerative architecture with BFSK modulation to improve speed and sensitivity. Transmitter efficiency is improved by using a power oscillator to directly drive the antenna. The entire transceiver achieves a total link energy less than 1nJ/b and can communicate over distances...
This paper presents a new zero-optimization scheme for noise-coupled ΔΣ analog-to-digital converters (ADCs). The proposed technique enhances the signal-to-quantization-noise-ratio (SQNR) by optimizing noise-transfer-function (NTF) zero locations to get maximum in-band noise shaping. The amount of SQNR improvement using the new scheme depends on the order of the modulator. Therefore, zero optimization...
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