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I think I was very fortunate to get a chance to work in microelectronics in its very early days. Those were very exciting times, particularly the day I found that I could build DRAM with just a single transistor and a capacitor. I wrote an internal paper and obtained a patent, but the first chance I had to work much on my idea came about four years later when the small team I worked with was challenged...
The effect of process variability on power and performance of integrated circuits can only be reduced with statistical optimization techniques. In this paper, we examine optimum VDD-VT design for minimizing power in deep-submicron CMOS circuits and introduce highly-efficient algorithm for yield constrained optimum power operation to include the impact of process variability and avoid the limitations...
In this paper forward body bias technique is implemented on a low noise amplifier to improve its noise figure and gain. The forward body bias is applied in the conventional Low-Noise Amplifier design which accounts for the low Noise-Figure and high Gain in it. The cascode LNA operating at 24 GHz without forward body bias is compared with the LNA having forward body bias using the PTM 65-nm technology...
In this paper an area and power efficient 56T 4-bit comparator design has been presented by using GDI technique. The proposed 4-bit comparator design consist of 28 NMOS and 28 PMOS. A GDI full adder module has been used to design this comparator which consumes less area and power at 120 nm as compared to previous full adder designs. The proposed 4- bit comparator design is based on this area and power...
A 5–20Gb/s power scalable adaptive continuous-time linear equalizer (CTLE) using edge counting is fabricated in 40-nm CMOS technology. The power of this CTLE is adjusted according to the bit rates to improve the power efficiency. An edge counting technique with an asynchronous clock is presented to adaptively adjust the gain and power of this CTLE. All the measured bit error rates are less than 10...
A neuron-MOS-based dynamic circuit scheme with two-phase clocks for realizing voltage-mode multiple-valued logic(MVL), is proposed. The dynamic ternary inverter, literal circuits, and quaternary inverter are designed, and the standard CMOS process with a 2-ploy layer is adopted without any modification of the thresholds. In the proposed circuits, the problem of floating output nodes is solved. The...
This paper proposed a CMOS circuit technique for realizing an electronically and linearly tunable transconductor for low-voltage low-power applications. The realization technique is achieved by squaring the transconductance gain (gm) of the CMOS OTA. Its input stage is design based on the dynamic threshold voltage transistor (DTMOS) for low-voltage, low-power transconductor. Its gm can be linearly...
The dynamic threshold MOSFET (DIMOS) in standard CMOS technology can be realized by connecting the body of a PMOS to the gate. The threshold voltage of a DTMOS transistor is reduced by forward bias of the source-body PN junction, making it possible to operate in low voltage circuits. In this paper, we propose a 1-V DTMOS-Based fully differential telescopic cascade OTA. The output swing and input common-mode...
There are several techniques available to control the leakage current in deep sub-micron technologies. One of the techniques is the Input Vector Control (IVC). By using IVC, leakage power consumption of a circuit can be minimized in the off state. In this paper, an algorithm has been given to calculate the best input vector that can be applied to the circuit (designed with 65nm technology transistors)...
Employment of high-k dielectric is one of the most important strategies to reduce operating voltage of an integrated circuit. This paper demonstrates experiments on organic FET and CMOS circuit where the dielectric layer was constructed of P(VDF-TrFE) and PS polymer dielectric. The dielectric constant of compound dielectric increased about three times in comparison with that of pristine PS. This contributes...
This paper presents an attractive approach for bandwidth extension of a four quadrant CMOS analog multiplier. The proposed approach is based on using dynamic threshold MOS transistor (DTMOS) which is an effective technique that achieves supply voltage reduction with a simultaneous increase in the overall transconductance of the MOS transistor. The proposed multiplier can operate at very high frequencies...
The wireless communication has led to the increased demand and relying on the batteries. For continuous striving on the low power operating in semiconductors and other technologies, batteries could be put back by the stand in sources involving the generation of the DC by RF energy harvesting techniques. In this paper we are modeling a CMOS harvester circuit and its analysis is realized at lower power...
A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate the RTN-related variation of the device drain current. The RTN parameters obtained from experimental traces are used to simulate the impact of RTN in the drain current of pMOS...
This paper proposes a pulse-controlled common-mode feedback circuit for a supply-scalable fully-differential amplifier. The pulse-controlled common-mode feedback circuit overcomes the large area cost associated with a conventional R-C common-mode feedback circuit while maintaining high gain and large output signal range of the amplifier. The amplifier is implemented in low power/leakage 65nm CMOS...
This paper demonstrates the design of analog amplifiers using alpha-power MOS model. Any MOS amplifier design begins with estimation of device parameters (NMOS/PMOS) like alpha($\alpha), V_T$ and device transconductance ($k^\prime$) and they are typically estimated from simple device plots using simulator. The approach proposed here assumes measured at of \SI{1}{\micro\ampere} from...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
The technique of maximizing image sharpness is a powerful means of adaptively correcting phase aberrations in wavefronts. Crucial to this correction is a sensor that provides an accurate real-time estimate of image sharpness. In this paper, we introduce a novel image sharpness sensor using CMOS active pixel technology that computes image sharpness at a sample rate of 7.8 kHz. The sharpness sensor...
A simple all CMOS low temperature coefficient current reference is designed. Two opposite temperature coefficient supply-insensitive self-bias reference generators that have a function of threshold voltage, mobility and resistor are utilizing to compensate the first-order and second-order temperature curvature. The proposed circuit is designed in AMI 0.5µm process with 5V supply voltage over the temperature...
This work proposes the use of non-recursive factored forms in material implication logic as a way to increase performance with a small additional cost in the number of required devices. Previous works addressing memristor based implication logic focus only on recursive forms. The utilization of factored forms can reduce the number of operations. Since this kind of logic is naturally sequential, the...
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