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Multi-gate architecture has been considered as one of the most viable alternatives to MOS devices scaling below 22 nm nodes [1] due to its stronger robustness to the short channel effects with respect to planar architectures. In short channel devices, the control of the gate over the channel charges dramatically decreases making the use of planar devices extremely challenging. Despite providing an...
We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (Wfin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that Wfin scaling effectively improved cut-off properties at Nd up to 5 × 1018 cm−3 and the electron mobility in the narrowest channel (Wfin =...
We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations (<100> or <110>). We evidence that pMOSFETs along <110> are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (−3GPa) and...
Introducing high-mobility channel materials such as Ge is an effective way to reduce the power supply voltage because its higher current drivability leads to lower gate-overdrive voltage under a given Ion spec. On the other hand, thin body and buried-oxide (BOX) Si-On-Insulator(SOI) MOSFETs have been intensively investigated in terms of better short-channel effects and efficient Vth controllability[1–4]...
As CMOS technology continues to scale down, allowing operation in the GHz range, it provides the opportunity of low cost integration of analog, digital and RF functions on the same wafer for System-on-Chip (SoC) applications [1]. SoC circuits on Si are prone to substrate losses and coupling, especially when RF analog and digital functions are integrated together into the same chip. In digital circuits,...
In this paper, the high-temperature performance of the commercial SiC power MOSFETs has been extensively evaluated beyond 125 °C - the maximum junction temperature according to the datasheet. Both the static and switching characteristics have been measured under various temperatures up to 200 °C. The results show the superior electrical performance of the SiC MOSFETs for high-temperature operation...
This paper presents a 7.5 kW liquid cooled three-phase buck rectifier which will be used as the front-end rectifier in 400 Vdc architecture data center power supply systems. SiC MOSFETs and SiC Schottky barrier diodes (SBDs) are used in parallel to obtain low power semiconductor losses. Input and output filters are designed and inductor core material is compared to reduce passive component losses...
Silicon Power MOSFETs, with more than thirty years of development, are widely accepted and applied in power converters. Gallium Nitride (GaN) power devices are commercially available in recent years [1], but the device performance and application have not been fully developed. In this paper, GaN devices are compared with state-of-art Si devices to evaluate the device impact on soft-switching DC-DC...
Recently, development and progress in information and telecommunications industry and service have gradually made significant increase in power consumption of Information and communication technology (ICT) equipment. To provide an energy-saving, floor space saving system solution for the data center or telecommunications, there exhibits a new trend moving towards high voltage power conversion. This...
A performance comparison of SiC MOSFETs and JFETs in a high-power (1kW) DC-DC converter to form part of a single phase PV inverter system is presented. The drive design requirements for optimum performance in the energy conversion system are also detailed. The converter which is based on 1.2kV 20A SiC switches and 600V 8A SiC diodes was tested under continuous conduction mode at frequencies up to...
Vision chips are natural candidates for being among the first areas that are able to utilize the emerging 3D integration possibilities. In some 2D vision chip architechtures there are pixel level AD and/or DA converters that are used for various purposes. This article covers the challenges and needs when targeting a megapixel architechture within a 1cm2 chip area. The Through-Silicon-Vias (TSVs) on...
Grating couplers using CMOS poly-silicon gate layer are demonstrated, which can be integrated with electronic circuits without adding any additional process steps. Peak coupling efficiency of ∼40% and 3dB bandwidth of ∼60nm are obtained with low back reflection.
Failure analysis on low yield cases revealed different degrees of fused polysilicon gate damage on specific CMOS circuit layout and device structure. Non-uniformity of plasma density during plasma related process has induced trapped charges in the gate oxide especially on circuit layout with large metal line perimeters and small poly gate structure. Trapped charges could become the catalyst to cause...
TEM dark-field off-axis electron holography technique was applied to study strain profile in bulk Si pMOSFETs with epitaxial SiGe selectively grown in source/drain are. Based on lattice displacement-induced electron wave phase shift, 2-D strain mapping (ε[110] and ε[001]) were retrieved. Strain variation due to sample thinning was evaluated. Results from dark-field holography technique was discussed...
We review the current status on DualChannel CMOS based on compressively strained SiGe channels for p-type and Si channels n-type MOSFETs: from the integration on fully depleted SOI wafers to the electrical performance (threshold voltage shift, low access resistance, large carrier mobility values...). Moreover SiGe layers are beneficial for tunnel FETs, specially for improving the ON current densities...
Single-crystal germanium (Ge) offers high electron and hole mobilities and is a viable candidate for channel materials in advanced metal-oxide-semiconductor field-effect transistors (MOSFETs). This work encompasses heteroepitaxial Ge growth on silicon (Si). The focus is on trench fill by undoped Ge as well as in situ Ge doping, both p-type and n-type. These aspects of epitaxial Ge growth play important...
High-frequency limit of Si single-electron transistor (SET) is investigated. Since the SETs inevitably have tunnel barriers, the operation speed is thought to be low. To measure the high frequency properties of SETs, we employed their special rectification characteristics, which occurred due to the asymmetry of Coulomb diamond when alternating current voltage was applied to the drain terminal. By...
The density of through-silicon-via (TSV) on CMOS chip is limited by TSV dimension and keep-out zone (KOZ). A high aspect ratio Cu TSV process, 2 µm × 30 µm, is demonstrated on 28nm CMOS baseline with good electrical performance and low cost. By implementing 2 µm × 30 µm TSV, the Si stress in the vicinity of TSV caused by thermal expansion is able to be relieved. It is, therefore, shown that the relaxation...
Main features of innovative Cyclic Selective Epitaxial Growth / Etch (CSEGE)processes developped in order to grow mushroom-free Si and SiGe:B Raised Sources and Drains on short gate length FD-SOI MOSFETs with imperfectly protected poly-Si gates.
The variation of saturation drain current (Id,sat), induced by the random dopant variation (RDF), has been extensively studied by a new multivariate analysis method. It was found that the variation of Id,sat is originated from Vth,sat and saturation velocity (Vsat), while the variation of Vth,sat comes from the drain induced barrier lowering (DIBL). However, the experimental results shows that Vsat...
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