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This paper describes a high-speed low-power subranging Flash ADC designed in 90nm Mixed-Mode CMOS process. The maximum speed of subranging-ADC is limited by the time taken for the fine-ADC reference to settle. The proposed method splits optimally the total time taken for the coarse-ADC and fine-ADC comparisons to achieve the maximum possible clock speed. An auxiliary track-and-hold has been used in...
This paper presents a technique called supply boosting for designing sub-1V analog/mixed-signal circuits. Supply boosting technique (SBT) is suitable for sub-micron CMOS processes containing MOSFET transistors with threshold voltages comparable to the supply voltage. SBT is based on the idea that if current consumption of the circuit block is very low, in the order of nanoamper, supply voltage could...
This paper presents the design and measurement results of an error ADC with a pipeline structure for DC-DC converter digital controller in 0.13μm technology. The proposed error ADC shared by three voltage rails through an analog MUX. The error signal is amplified by a differential amplifier and a switched capacitor amplifier with a total gain of 10. The amplified error signal is then digitized with...
An 8-bit subrange Analog to Digital Converter (ADC) designed in a CMOS TSMC90nm process consisting of a coarse 4-bit and a fine 4-bit ADC stage is presented in this paper. It occupies only 0.04mm2 of die area and dissipates less than 22mW without sacrificing speed since the sampling rate is higher than 500MS/s and the achieved SNDR is higher than 40dB. These features have been estimated by post-layout...
In this paper, a digital calibration algorithm for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The spice simulation result shows the digital foreground calibration algorithm can efficiently improve the linearity of the ADC.
A 9-bit, 125MSPS, power scaleable MDAC applied in high performance pipelined ADC in 1.8V supply voltage, 0.18um CMOS process is presented in this paper. The related circuits: a high gain, high unit gain bandwidth operational amplifier with gain boosting, common-mode feedback and bootstrap are proposed. Additionally, when the sampling rate is changed, the power of the whole MDAC can be significantly...
In this paper, a design for low power flash ADC with configurable resolution is proposed. A novel sub flash architecture is employed to achieve variable resolution as well as to switch the unused parallel voltage comparators and resistor bias circuit to standby mode leading to the consumption of only leakage power. The ADC is capable of operating at 4-bit, 6-bit and 8-bit precision and at a supply...
There is a need to use a truly adaptive analog-to-digital converter (ADC) to respond to any signal change and reduce the power consumption with less implementation complexity. The paper presents a front-end ASIC implementation for an adaptive control unit (ACU) for a reconfigurable ADC. The control unit is based on an adaptive algorithm that changes either the converter resolution or sampling-rate...
In this paper a low power CMOS Comparator is proposed which is very well capable of distinguishing DC voltage difference of around even 0.2 mV. By providing excitory feedback, the proposed compact circuit is made to successfully avoid the need of a post amplifier or any other cascading stages. The circuit can also operate at a wide range of power supply starting from 1.1 V with a clock frequency of...
A third-order switched capacitor delta sigma ADC is implemented in SMIC 0.18-μm CMOS technology for low frequency applications. By adopting feedforward architecture, the loop stability can be improved, and the output swing of integrators can be suppressed significantly, thus improving the linearity. In order to provide stable operation for the modulator, oscillation detecting circuit is employed to...
A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS. The design utilizes a background timing skew calibration technique to improve dynamic performance, and comparator offset calibration to reduce power dissipation. The experimental prototype achieves an SNDR of 25.1 dB at Nyquist and 27.5 dB for low frequency inputs. The circuit occupies an active area of 0.44 mm2 and consumes 81...
This paper presents a 10-bit SAR ADC using a variable window function to reduce the unnecessary switching in DAC network. At 10-MS/s and 1-V supply, the ADC consumes only 98 μW and achieves an SNDR of 60.97 dB, resulting in an FOM of 11 fJ/Conversion-step. The prototype is fabricated in a 0.18μm CMOS technology.
In this report, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with current-mode single-ended amplifier, this OTA reduce parasitic taking by gain-boost amplifier to achieve high-gain and high-speed. Besides, a dual phase SC-CMFB circuit is introduced, and some methods are concerned to improve the performance. Then, by optimization the layout design,...
This paper presents the design of a DFE for a 2x blind ADC-based RX. The DFE is implemented in 65-nm CMOS along with a 2x blind CDR and ADC. Our measured results confirm 5Gb/s data recovery with BER less than 10-12 with a channel introducing 13.3dB of attenuation at the Nyquist frequency of 2.5GHz. Without the DFE, the BER exceeds 10-8.
A 12b 50MS/s ADC is presented that pipelines a first stage 6b MDAC with a second stage 7b SAR ADC. The first stage uses a low-power SAR architecture for the sub-ADC, to achieve the large 6b stage resolution. A “half-gain” MDAC reduces the output swing and increases the closed-loop bandwidth of the op-amp in the first stage. This ADC consumes 3.5mW from a 1.3V supply, achieves an ENOB of 10.4b at Nyquist,...
A 300MHz all-digital differential VCO-based ADC occupies 0.02mm2 in 65nm CMOS, achieving a peak SFDR of 79dB and an SNDR of 64dB over a 30MHz BW. This high linearity is obtained using two VCOs in differential configuration in combination with an 11-points digital calibration. The power consumption is 11.4mW and the FOM is 150fJ/conv. step.
This paper describes an activity-dependent intracortical microstimulation system-on-chip (SoC) that can convert extracellular neural signals recorded from one brain region to electrical stimuli delivered to another brain region in real-time. The system integrates an analog recording front-end with input noise voltage of 2.6μVrms in 10.5kHz bandwidth, 5.5μW 10b SAR ADC, 750nW digital spike discrimination...
This paper presents a low power CMOS nuclear magnetic resonance (NMR) receiver chip for monitoring of small tissue samples within the human body. We present preliminary results from a prototype spectrometer focused on the phosphorus (31P) spectra operated in a 5 Tesla B0 magnet. The prototype, fabricated in a 130nm CMOS technology, occupies an active area of 0.215mm2 and consumes 4mA from a single...
A 7-bit 360° phase rotator in 45nm CMOS interpolates between coarse phases by modulating the injection point of an oscillator. This architecture decouples phase resolution from device sizing. INL and DNL are improved by independently adapting the delay of each oscillator stage. A digital phase-locked loop using a time-to-digital converter based on a tracking ADC keeps the oscillator tuned to the injection...
A 4.23-bit, high speed comparator for high-speed flash analog-to-digital converter and X-band applications that can work at a sampling rate of 12.5GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The BiCMOS...
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