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Recently, radiation-hardened static random access memory (SRAM) - based field programmable gate arrays (FPGAs) are available for use in space radiation environments. Although such radiation-hardened SRAM-based FPGAs are programmable, the uses of radiation-damaged SRAM-based FPGAs are not allowed as well as application specific integrated circuits (ASICs). Their serial configuration is invariably damaged...
Reconfigurable embedded devices built on SRAM-based Field Programmable Gate Arrays (FPGA) are being increasingly used in critical embedded applications. However, the susceptibility of such memory cells to Single Event Upsets (SEU) requires the use of fault tolerant designs, for which fault injection is still the most accepted verification technique. This paper describes FIRED, a fault injector targeted...
Soft error induced reliability problem has already become a major concern for modern SRAM-based FPGAs (Field Programmable Gate Arrays) even at the ground level. In this paper, we propose a duplication-with-recovery (DWR) technique to recover the configuration bit faults on interconnects, which contribute to the majority of soft errors in FPGAs. Based on a study on the detailed routing structure in...
In this paper, an indirect matrix converter (IMC) which makes directly ac-ac power conversion, is modeled and simulated in real-time to demonstrate the capability of the new link between Opal-RT's eHS (electric Hardware Solver) and the CAD tool PSIM. An automatic methodology for the real-time simulation of power converters from PSIM circuit designs to FPGA is presented and discussed. A time-step of...
FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been...
Systems based on Xilinx Virtex series FPGAs can benefit, compared to traditional rad-hard technologies, from high performance, high logic density and dynamic reconfiguration capability. However, the underlying SRAM technology is sensitive to ionizing radiation, which can induce faults that must be managed to improve system's dependability. This paper proposes a Dual-Layer Fault Manager concept, which...
FPGA-based multiprocessors, referred as softmultiprocessors, have an increasing use in embedded systems due to appealing SRAM features. More than 95% of such FPGAs are occupied by SRAM cells constructing the configuration bits. These SRAM cells are highly vulnerable to soft errors threatening the reliability of the system. This paper proposes a fault-tolerant method to detect and correct errors in...
As device size shrinks, SRAM-based FPGAs are increasingly prone to be affected by single-event upsets (SEUs). SEU mitigation techniques for FPGAs are mostly expensive in terms of area and power costs. This paper proposes a new design for FPGA hardening using dual-modular redundancy (DMR). The duplication operates on lookup-table (LUT) level, and each pair of identical LUTs will be voted by an AND...
Recently, existing radiation-hardened static random access memory (SRAM)-based field programmable gate arrays (FPGAs) are anticipated for use in space radiation environments. Although such radiation-hardened SRAM-based FPGAs are programmable, the use of a radiation-damaged gate array has never been assessed for use with application-specific integrated circuits (ASICs) because its serial configuration...
TMR is a very effective technique to mitigate SEU effects in FPGAs, but it is often expensive in terms of FPGA resource utilization and power consumption. For certain applications, Partial TMR can be used to trade off the reliability with the cost of mitigation. In this work we propose a new approach to build Partial TMR circuits for FPGAs using approximate logic circuits. This approach is scalable,...
Fault-tolerance is becoming an essential feature in the design of Networked Control Systems (NCSs). Furthermore, Sensor-to-Actuator (S2A) architectures have shown some advantages over conventional In-Loop architectures. This paper focuses on fault-tolerant controllers in the context of S2A systems. It proposes the use of Triple Modular Redundancy at the controller level. The fault-tolerant controller...
This paper presents a novel stream processor architecture for SRAM-based FPGAs that is specifically targeted at payload data processing and which employs innovative Fault Detection, Isolation and Recovery (FDIR) mechanisms to cope with failures caused by radiation effects. As part of this FDIR strategy, an availability analysis method is developed that is able to predict the steady state availability...
Physically Unclonable Functions (PUFs) are introduced to remedy the shortcomings of traditional methods of secure key storage and random key generation on Integrated Circuits (ICs). Due to their effective and low-cost implementations, intrinsic PUFs are popular PUF instances employed to improve the security of different applications on reconfigurable hardware. In this work we introduce a novel laser...
The description of equipment and methods used for conducting ionizing radiation Accelerated Life Testing (ALT) of programmable hardware, especially Field Programmable Gate Arrays (FPGA) at the cyclotron is introduced. Methodology of testing and Single Event Effects (SEE) detection and online monitoring is described together with some results of testing several SRAM and Flash based FPGAs. In the course...
Scaling trends of reconfigurable hardware (RH) and their design flexibility have proliferated their use in dependability-critical embedded applications. Although their reconfigurability can enable significant fault tolerance, due to the complexity of execution time in their design flow, in-field reconfigurability can be infeasible and thus limit such potential. This need is addressed by developing...
The existing intentional electromagnetic interference (IEMI) fault injection method based on continuous sinusoidal wave has a difficulty in injecting faults at a specific operation or time. This means that the obtained faulty outputs do not always satisfy a specific condition (e.g., time or number of error bytes) for performing fault analysis such as differential fault analysis (DFA). This paper presents...
Being the first five-terminal Modular Multilevel Converter (MMC)-based HVDC project in the world, the control and protection system must be validated under various operation modes as well as contingency at the factory acceptance test. This paper presents the configuration and performance of a hardware-in-the-loop (HIL) test platform that is based on a multi-rate real-time simulator using commercial-off-the-shelf...
The impact of SRAM-based FPGAs is constantly growing in aerospace industry despite the fact that their volatile configuration memory is highly susceptible to radiation effects. Therefore, strong fault-handling mechanisms have to be developed in order to protect the design and make it capable of fighting against both soft and permanent errors. In this paper, a fully reconfigurable medium-grained triple...
Reliability is a major design constraint for critical applications. SRAM-based FPGAs are attractive to critical applications due to their high performance and flexibility. However, they are high susceptible to radiation effects such as soft errors. Memory scrubbing is an effective method to correct soft errors in SRAM memories but it imposes an overhead in terms of logic area and energy consumption...
FPGAs are becoming more popular in the domain of safety-critical applications (such as space applications) due to their high performance, re-programmability and reduced development cost. Such systems require FPGAs with self-detection and self-repairing capabilities in order to cope with errors due to the harsh conditions that usually exist in such environments. In this paper, a new dynamic fault recovery...
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