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A sub- ECG acquisition IC is presented for a single-chamber leadless pacemaker applications. It integrates a low-power, wide dynamic-range ECG readout front end together with an analog QRS-complex extractor. To save ASIC power, a current-multiplexed channel buffer is introduced to drive a 7 b-to-10 b self-synchronized SAR ADC which utilizes 4 fF/unit capacitors. The ASIC consumes only 680nA...
The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.
The crosstalk between stripline and the power plane on an adjacent layer in a multilayer printed circuit board (PCB) are analyzed and shown. Different methods of suppressing this crosstalk effect are discussed and compared.
DC/DC converters are widely used to provide various power supply voltages required for many electronic components on a board. Though DC/DC converter is more efficient than the linear regulator is, however, the switching noise becomes larger with the increase of the switching frequency. In particular, ringing noises at the sharp rising edge of the switching waveform occurs by the effect of the parasitic...
This paper demonstrates an on-die STO thin film decoupling capacitor used for resonant power supply noise reduction. The on-die STO capacitor consists of STO whose dielectric constant is about 20 and is sandwitched by Cu films in an organic interposer on which we can also draw connection wires by Cu deposition. The capacitor was attached directly on our test chip using ball banding technique through...
A low-voltage differential signaling (LVDS) driver with 3-bit programmable slew-rate control has been designed and fabricated in 0.13um complementary metal oxide semiconductor (CMOS) process. On-chip programmable capacitors allow cost saving compared to external capacitors and fine tuning to driver output slew-rate. This enables system designers with the flexibility to optimize driver slew-rate for...
In this paper, we present a noise-immune high-speed motion detection CMOS image sensor. The proposed architecture is quite appealing for motion object tracking applications as it can detect motion with a high immunity to random noise. Our pixel has a front-end event generator to detect and convert temporal light intensity changes into binary events. By on-chip implementing an event-clustering algorithm...
This paper concerns the design and the implementation of a transimpedance amplifier (TIA) dedicated to detector of Near Infrared spectroscopy (NIRS). To reduce the effect of the input capacitance on the bandwidth, a bias circuit with low input impedance is connected to input stage. A single ended common source common gate input stage based on a cascode structure is used to get a higher gain bandwidth...
A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB...
In this paper, we demonstrate our STO thin film decoupling capacitor embedded in organic interposer is effective for reduction of resonant power supply noise of LSI. By comparison of Shmoo plots with on-chip MOS capacitor, significant contributions of STO capacitor to higher operable frequency and lower power supply voltage are shown.
The electromagnetic interference (EMI) filter plays an important role in the EMI noise suppression. As the development of the switch mode power supply (SMPS), the power density of the SMPS improves every year. As a result the distance between components becomes smaller and smaller. The near-field magnetic coupling between components becomes larger and larger. However there are fewer studies about...
In the design of high complexity systems, the significance of signal integrity plays a vital role and in turn depends on the occurrence of different noises such as crosstalk noise, reflection noise, switching noises and active periodic noise. These noises are more in the design of IC, PCB layout design and multilayered PCB. However the impact of Simultaneous Switching Noise (SSN) noises in a IC with...
Since the loss of input rectifying diode bridge in the conventional PFC converter reduces the efficiency, the bridgeless PFC converter has been proposed. The totem-pole bridgeless PFC converter is the most representative one. However the common mode noise current occurring around the input voltage zero-crossing brings severe EMI problem restricts its practical application. In order to improve noise...
Power supply noise is a serious issue for advanced CMOS LSIs and systems, since the performance of LSI chip is becoming more sensitive to power supply fluctuation under the lower power supply voltage. Because power supply noises are strongly related to the anti-resonance peak frequency in the total power distribution network (PDN), suppressing the anti-resonance peak is one of the most important design...
A chopped capacitively-coupled instrumentation amplifier (CCIA) with a proposed duty-cycled Gm-C DC servo loop (DSL) for bio-potential signal acquisition is presented. The proposed architecture realizes a large time constant with small circuit area without sacrificing noise and power performance. Furthermore, this pseudo-resistor-less design grants this architecture easily portable for more advanced...
We present a 56-channel neural recording interface with a chopper-stabilized DC-coupled front-end and a programmable mixed-signal DC cancelation feedback. Each recording channel has a fully-differential amplifier with 51–54dB of gain, an input-referred noise of 5µVrms integrated from 10Hz to 5kHz and a CMRR of 65dB. Input DC-coupling allows for a simple chopping scheme without the area overhead of...
Power loss at the output stage of conventional constant current neural stimulators is notably high. This is particularly disadvantageous for applications in implantable systems where power budget is limited. We present a novel electrical stimulator architecture for significantly reduced power loss and low noise operation. The system generates a calibrated output voltage profile for driving electrode...
A novel method of using complementary split-ring resonators (CSRRs) structure in power/ground plane pair for wideband simultaneous switching noise (SSN) isolation is presented. Compared with traditional mushroom-like electromagnetic band gap (EBG) and coplanar EBG, the proposed nested CSRRs structure only need to be partially etched on the power plane and is easy to be fabricated, while the performance...
This paper presents a two stage low noise chopper amplifier for integrated angular acceleration sensor signal processing circuit which consists of amplifiers, phase-locked loop and automatic gain control. Capacitor feedback amplifier circuit is one of the most suitable for CMOS technology however capacitor amplifier with chopped op-amp has poor low frequency performance because of parasitic resistive...
In this paper the common-mode noise generation mechanism and its suppression is presented for the hard-switched isolated full-bridge forward topology. Due to the extensive interleaving of primary and secondary windings, such transformers exhibit large inter-winding capacitance which is the well-known cause of large common-mode noise current in the converter. Therefore, the effect of this large coupling...
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