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In this paper authors present a new method to organize hardware search in the tables of rules in the software defined network (SDN) switch. This paper describes the design features of modern SDNs based on open standard OpenFlow, main problems of modern OpenFlow switches, and proposes a new approach for building hardware search based on field-programmable gate arrays (FPGAs). The proposed method allows...
Node location information in wireless networks can be of a great virtue to many applications. Some require absolutelocation information, which may considerably increase the cost and complexity of the node design and operation, while others can suffice with relative location estimation. In order to achieve acceptance localization accuracy, most existing techniques either require additional costly ranging...
Wireless sensor networks (WSN) can be widely used in many areas, such as environment monitoring, weather forecasting, traffic control, etc. The wormhole attack problem is an important issue in WSN since it causes many problems, such as routing error, a reduction in sensor lifetime and broken network topology. Several wormhole detection approaches have been proposed, but most of them need special hardware...
For SDN hybrid network topology, this paper builds a relationship model of SDN hybrid network flow and capacity based on cross entropy, and makes quantitative analysis and simulation about packet arrival rate normalized probability transmitted by the OpenFlow switches on the ith link. Seen from the results of the analysis, the probability can be up to 66.17%, and this arrival rate of packets can not...
A Field-Programmable Gate Array (FPGA) is an integrated circuit that allows users to program product features and functions after manufacturing. Verilog-to-Routing (VTR) is an open source CAD tool for conducting FPGA architecture and CAD research and development. As one of the core tools of VTR, Odin II is responsible for Verilog elaboration and hard block synthesis. This project describes the improvements...
The CPU based software simulator for neuromorphic computing is faced with problems of high power consumption and speed limitation of interconnection network, especially in large-scale Spiking Neural Network (SNN) simulation. IBM, Stanford, and ARM have demonstrated us their solutions for neuromorphic computing. However, the cost and development cycle make these approaches impractical for general research...
In typical settings for Wireless Sensor Networks (WSNs), a potentially large set of nodes operates under strict requirements concerning energy consumption and packet delivery success. If non-reliable or even malicious nodes participate, standard protocols can suffer in performance which may result in a limited functionality of the whole network. This paper addresses this issue by establishing end-to-end...
BXI, Bull eXascale Interconnect, is the new interconnection network developed by Atos for High Performance Computing. In this paper, we first present an overview of the BXI network. The BXI network is designed and optimized for HPC workloads at very large scale. It is based on the Portals 4 protocol and permits a complete offload of communication primitives in hardware, thus enabling independent progress...
Pattern matching is used in most of the network security devices in order to detect attacks, threats and malicious network traffic. Many hardware architectures have been designed to accelerate this time-critical operation in order to increase processing speed and achieve multi-gigabit throughput. Recently introduced automata processor is an powerful architecture which represents a new class of field...
In this paper we propose a distributed routing algorithm for networks-on-chip (NoCs) that can dynamically detect permanent failures in NoC links and recalculate routing paths using healthy links. What sets the proposed methodology apart from the previous works is that it provides a better tradeoff point between the improvement in fault tolerance and performance penalty due to the required redundancy...
Routing protocols in Wireless Sensor Network (WSN) are responsible for propagating and coordinating of information transfer from one end of the network to the other. Dynamic Window Secured Implicit Geographic Forwarding (DWSIGF) is a robust, cross layer, security bound routing protocol that propagates information in a multi-hop network using the greedy and random forwarding strategies. These strategies...
The increasing computation requirements of multimedia and streaming applications demand high parallel processing capabilities. Hence modern computer architectures focus on integrating more processing cores into a single chip to achieve higher parallelism and processing capability. These processing cores rely on sophisticated on-chip network to communicate among others. Accordingly, this paper provides...
Reliability is an important concern in many Field Programmable Gate Array (FPGA) based designs, mainly in applications which must be free of faults, and need to be available for long periods of time. Triple Modular Redundancy (TMR) is a well known approach for a system to tolerate possible faults, but a permanent fault in the TMR hardware may diminish the redundancy advantage. In this paper, we present...
Robocar World Championship or briefly OOCWC is a new initiative to create a community of people who share their interest in investigating the relationship between smart cities and robot cars with particular attention to the spread of robot cars in the near future. At the heart of this initiative is the Robocar City Emulator. It is intended to offer a common research platform for the investigation...
Openflow provides a key step in abstracting network functions by separating the control and the forwarding plane. However, current rather rigid switches constrain packet processing programmability. It is therefore complex to implement flexible packet classification within existing ASIC-based switches, especially when forwarding switches rely on a restricted set of tables. In this paper, we introduce...
NoC based high performance MP-SoCs can have multiple secure regions or Trusted Execution Environments (TEEs). These TEEs can be separated by non-secure regions or Rich Execution Environments (REEs) in the same MP-SoC. All communications between two TEEs need to cross the in-between REEs. Without any security mechanisms, these traffic flows can face router attacks in REEs. Both routing table and routing...
We report the experimental assessment of a hybrid control plane for multi-domain, heterogeneous networks based on abstraction and hierarchical TE. A mesh of SDN controllers use GMPLS protocols as East/West interfaces, forming an abstracted topology.
Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed...
Implementing applications on Reconfigurable Computing Architectures (RCAs) is an important research topic because of their high potential to accelerate a wide range of functions. Nevertheless, configuring and programming RCAs is a long-standing challenge. In this paper, we propose a design methodology to map an algorithm on an FPGA preconfigured with a Coarse-Grained Reconfigurable Architecture (CGRA)...
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