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This paper proposes an area-efficient partial-sum generator (PSG) architecture for polar decoder implementation. High-throughput PSG designs mainly consist of an encoding matrix generator and a partial-sum update circuit. The matrix generator conventionally is built by cascading a series of D flip-flops and XOR gates. By decomposing the target matrix into the Kronecker product of smaller matrices,...
In this paper, we consider a new architecture for mobile systems to effectively accommodate mobile cloud computing traffics in conjunction with conventional delay-limited traffics (e.g., voice traffics). It is assumed that small base stations (BSs) do not decode cloud data streams from a user, but forward the received signals from the users to a cloud server (CS), while small BSs are to decode conventional...
The speed of market data processing is a key factor to grab the gains and losses of instant trading profits. Typically, the market data processing systems are deployed on software platforms, which introduce high and unpredictable processing latencies. In this paper, we propose a scalable architecture for low-latency market-data processing on Field Programmable Gate Array (FPGA). A market-data processing...
In simultaneous wireless information and power transfer (SWIPT), practical receiver architectures consisting of an information receiver and an energy harvester have been proposed in place of an ideal receiver capable of performing two tasks simultaneously using the same circuits. In this paper, we present a novel receiver architecture design incorporating an interplay between the information receiver...
This paper proposes the design of an 8-bit segmented current steering (CS) digital to analog converter (DAC), which uses Chinese abacus technique to improve both static and dynamic performances. Chinese abacus DAC is simple, occupies less area and shows better linearity compared to binary DAC. In conventional segmented CS architecture, the MSB is implemented in unary and LSB is implemented in binary...
Traditionally, serial scan architecture have been predominantly used as a DFT technique for most of the designs. However, shrinking technology and increasing design complexity has brought a set of new test challenges. It initiates new research direction to explore innovative DFT architecture. This paper proposes a new DFT architecture, named as Joint-scan. The proposed architecture provides a solution...
Digital-to-Analog converter (DAC) is a fundamental device in data processing systems. It serves as a conversion interface to reconstruct the analog signal from the digital output of the signal processors. In this work, the design and implementation of a 10-bit Segmented Current Steering DAC is carried out at 500 MHz clock frequency and 1.2 V supply voltage. The Segmented architecture provides the...
In the decoding of the Bose Chaudhuri Hochquenghem (BCH) codes, the most complex block is the Chien search block. In the decoding process of the BCH codes, error correction is performed bit by bit, hence they require parallel implementation. The area required to implement the chien search parallel is more, hence strength reduced parallel architecture for the chien search is presented. In this paper,...
Polar codes have become one of the most attractive topics in coding theory community because of their provable capacity-achieving property. Belief propagation (BP) algorithm, as one o f the popular approaches for decoding polar codes, has unique advantage of high parallelism but suffers from high computation complexity, which translates to very large silicon area and high power consumption. This paper,...
Online compression of I/O-data streams in general purpose computing will enhance the effective I/O bandwidth of processors, the bandwidth of the computer network as well as the storage capacity and the read/write performance of the storage. In this paper, a self-adaptive dynamic partial reconfigurable architecture for the online compression of data streams is introduced. The proposed architecture...
This paper presents an efficient hardware design approach for list successive cancellation (LSC) decoding of polar codes. By applying path-overlapping scheme, for LSC with list size l (l > 1), the l instances of successive cancellation (SC) decoder can be cut down to only one. This results in a dramatic reduction of the hardware complexity without any decoding performance loss. We also develop...
We propose a low-complexity implementation architecture for turbo product code (TPC) suitable for next-generation fiber optic networks (e.g. ≳ 100 Gb/s). The proposed code makes use of expurgated Bose-Chaudhuri-Hocquenghem (BCH) codes to improve the performance and reduce implementation complexity. In comparison with existing solutions, our results show that the propos d TPC architecture is able to...
Online compression of I/O-data streams in Custom Computing Machines will enhance the effective network band-width of computing systems as well as storage bandwidth and capacity. In this paper a self-adaptive dynamic partial reconfigurable architecture for online compression is proposed. The proposed architecture will bring new possibilities in online compression due to its adaptivity to dynamic environments...
High Efficiency Video Coding (HEVC) in-loop filtering includes the deblocking filter (DF) and the sample adaptive offset filter which consume about 20% of the total HEVC de coding time. In this paper a very energy efficient programmable multicore coprocessor for HEVC in-loop filtering is proposed. The coprosessor is placed and routed using leading edge 28nm technology to show that it can be clocked...
As modern high performance computing systems have various ICs associated together, one of the most appreciated architecture is direct path passing through the intermediate chips. Inter-chip and intra-chip communication are linked together in this architecture. Therefore to remove crosstalk induced noise and improve signal integrity, a novel CAC and corresponding CODEC which can be applied for both...
In this paper, we propose a 3-phase polar codes Successive Cancellation (SC) decoder. Benefiting from the local properties of the decoding tree, 3 zones are defined and associated to 3 distinct sub-decoders. This approach reduces the memory footprint while guaranteeing a better scalability in comparison with state of the art SC decoders. Several 3-phase SC decoders are implemented on an FPGA circuit...
Conventional bit-flipping (BF) algorithms spectacularly fail to handle punctured LDPC codes as they use hard decisions and, therefore, they cannot effectively cope with zero-reliability punctured symbols. However, BF techniques lead to low-cost high-speed decoders. This paper introduces a novel method that enables the use of BF-based iterative decoders for punctured LDPC codes. An erasure preprocessor...
Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures are mandatory. State-of-the-art decoding algorithms result in architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall...
The design of efficient wireless fronthaul connections for future heterogeneous networks incorporating emerging paradigms such as heterogeneous cloud radio access network (H-CRAN) has become a challenging task that requires the most effective utilization of fronthaul network resources. In this paper, we propose and analyze possible solutions to facilitate the fronthaul traffic congestion in the scenario...
Iterative decoding algorithms for low-density parity check (LDPC) codes have an inherent fault tolerance. In this paper, we exploit this robustness and optimize an LDPC decoder for high energy efficiency: we reduce energy consumption by opportunistically increasing error rates in decoder memories, while still achieving successful decoding in the final iteration. We develop a theory-guided unequal...
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