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The emerging security threats in the IC supplychain do not only challenge the chip integrity, but also raiseserious concerns on hardware IP piracy and reverse engineering. The existing register-transfer level (RTL) hardware obfuscationmethods insert a key sequence in the control and data flowto prevent the attacker from accessing the normal operationmode of a chip, rather than protecting the state...
Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However,...
For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices...
This paper proposes an area-efficient partial-sum generator (PSG) architecture for polar decoder implementation. High-throughput PSG designs mainly consist of an encoding matrix generator and a partial-sum update circuit. The matrix generator conventionally is built by cascading a series of D flip-flops and XOR gates. By decomposing the target matrix into the Kronecker product of smaller matrices,...
In this growing digital world all digital circuits are facing the issue of large power dissipation, higher packaging density, lower latency and higher degree of reliability. Today all the portable and hand held devices are aiming to have all the above said features along with greater battery life. One of the basic circuits that is mostly used in digital designs is multiplier. Now we have lot of different...
This document presents the contents and didactic methodology followed through the Digital Electronics course, imparted during the fifth semester of the Grado en Ingeniería Electrónica Industrial y Automática (Rama Industrial) at Universidad de Extremadura. Lab sessions reinforce all the theory contents of the course, providing the student with the experience of designing a microprocessor (with didactic...
Duty cycling has been the main concept for saving energy in sensor networks for a long time. Yet, additional overhead for synchronization and the fact that overhearing and idle listening cannot completely be prevented, motivated further research. Wake-up receiver, i.e., additional ultra-low power radios that are not switched off and can receive a so called wake-up signal, aim to fill this gap. The...
The Serial-out bit-level multiplication scheme is characterized by an important latency feature. It has an ability to sequentially generate an output bit of the multiplication result in each clock cycle. However, the computational complexity of the existing serial-out bit-level multipliers in $GF$<alternatives><inline-graphic xlink:type="simple" xlink:href="abdulrahman-ieq1-2456023.gif"/></alternatives> ...
In this paper, we have implemented high performance FPGA based pipelined tree architectures for a combined unsigned and two's complement comparator, and an equality comparator which checks whether the sum of two numbers is equal to a third number. The comparator architectures deviate from the combined Look-Up Table (LUT) and carry chain based implementation which is inferred by the Xilinx Synthesis...
A new method of high-level test generation for control faults in digital systems is proposed. High-level faults of any multiplicity are assumed to be present, however, there is no need to enumerate them. A novel concept of test groups which has the goal to prove the correctness of a part of the system's functionality instead of keeping track of fault coverage during test generation as in the traditional...
As more sensitive data are shared, transmitted, and stored on electronic devices, data security has become an important concern. Encryption algorithms that are safe against software-based attacks still face security threats from side channel attacks. For example, an encryption device's power consumption or operational timing can be correlated to the data being processed by the device, which can give...
The heavy reliance on third-party resources, including third-party IP cores and fabrication foundries, has triggered the security concerns that design backdoors and/or hardware Trojans may be inserted into fabricated chips. While existing reverse engineering tools can help recover netlist from fabricated chips, there is a lack of efficient tools to further analyze the netlist for malicious logic detection...
Recent years have witnessed a massive growth of global data due to the ubiquitous internet-of-thing products, social networking services, and mobile devices. Fast database analytics, therefore, has been increasingly attractive to numerous research. In this paper, a low-latency FPGA-based Database Processor (DBP) using bitmap index is proposed. By exploiting available embedded memory blocks and logic...
Low swing/voltage clocking is a well-studied approach to reduce dynamic power consumption in clock networks. It is, however, challenging to maintain the same performance at scaled clock voltages due to timing degradation in the Enable paths that are required for clock gating, another highly popular method to reduce dynamic power. A useful skew methodology is proposed in this paper to increase the...
Soft processors have a role to play in easing the difficulty of designing applications into FPGAs for two reasons: first, they can be deployed only when needed, unlike permanent on-die hard processors. Second, for the portions of an application that can function sufficiently fast on a soft processor, it is far easier to write and debug single-threaded software code than to create hardware. The breadth...
Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using emerging technologies such as quantum dot cellular automata. Earlier work uses traditional designs for sequential circuits and replaces the flip-flops and the gates with their reversible counterparts. Our earlier work used a direct feedback method without any flip-flops,...
This work proposes asynchronous interleaved scan architecture (AISA) intended for the internal structure of online Built-in Self-test for Null Convention Logic (NCL) circuits. NCL is a robust asynchronous paradigm which can target devices for long-life missions and hard-to-access environments. However, on-line self-test methods adapted to match the characteristics of this important asynchronous method...
Laser Fault Injection (LFI) is a powerful method of introducing faults into a specific area of an integrated circuit. Because the minimum spot size of the laser spot is physically bounded, many recent publications investigate down to which technology node individual transistors can be targeted. In contrast, we develop a novel attack that is applicable even when a large number of gates is affected...
The most compact implementation of the AES-128 algorithm was the 8-bit serial circuit proposed in the work of Moradi et. al. (Eurocrypt 2011). The circuit has an 8-bit datapath and occupies area equivalent to around 2400 GE. Since many authenticated encryption modes use the AES-128 algorithm as the underlying block cipher, we investigate if they can be implemented in a compact fashion using the 8-bit...
Verification is an essential step of the hardware design lifecycle. Usually verification is done at the gate level (Boolean level). We present verilog2smv, a tool that generates word-level model checking problems from Verilog designs augmented with assertions. A key aspect of our tool is that memories in the designs are treated without any form of abstraction. verilog2smv can be used for RTL verification...
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